Multi-core Processors Computing And Communication Module Design Between Nuclear Research

With more significant performance compared to single-core processors, and wider range of generality and flexibility compared to ASICs, multi-core processor systems have become the main developing trend of processor market these years. From the early personal computer area to competitive portable electronic device market, dual core processor and four-core processor already have been used widely. Due to the features of portable electronic devices, high-performance and low-power consumption have become the target of both industry and academic. Consistent with traditional processors, multi-core processors still pursue the computing efficiency of single unit. However, multi-core processors need to allocate different parts of the task onto several processing units based on the features of the applications, and the data sharing and synchronization between multiple cores becomes a key issue. As a result, inter-core communication technology is a key to the performance of multi-core systems. Although there have been a lot of research achievements in multi-core area, there is no optimal or unified architecture due to complexity of the system and diversity of the applications, which means there are still a lot of contents and directions worth exploring.Concentrating on communication and multimedia applications, and based on analyzing and learning from many other excellent works, this paper has proposed several design methods to improve computing and communication efficiency. The paper has included the design of computing modules of first tape-out generation multi-core processor and execution computing array used in second generation processor. This thesis also pays attention to inter-core communication mechanisms in multi-core systems. Furthermore, this paper introduces high-performance, low-power backend design flow under TSMC65nm technology. Details are as follows:(1) SIMD computing units and execution computing arrayThe RISC processor we designed uses MIPS324KE as a design reference and partly compatible with MIPS32instruction set, and extends computing modules including MDU, ALU and Shifter and corresponding instructions to improve data parallelism and power efficiency.To address the problems of inefficiency of some specific computations in communication and multimedia applications, taking H.264and LTE as main references, an execution unit array is proposed by extracting some accelerating units based on the analysis of applications. Different configurations need to be done according to the corresponding programs. as a result the programs can be processed more efficiently.(2) Reconfigurable register files and FIFO mapping mechanism for inter-core communicationIn this paper, traditional register files is extended using register banks. As a result, accesses to outside memories have been reduced greatly. In this way, computing and power efficiency is greatly increased.As to inter-core communication, message-passing mechanism is adopted based on2-D mesh NoC structure. Besides the communication mechanism of mapping FIFO to memory address space, another mechanism which maps FIFO to register file address space is also adopted in our design,. As a result, computing results will be transported through router to destination processors directly, which avoid memory accesses in an efficient way.(3) Advanced backend design flow under TSMC65nm technologyBesides the SIMD architecture, extended register file and two kinds of clock gating techniques in front end design of the processor, optimization is also adopted in backend design. Using multi-Vt design flow supported by TSMC65nm technology and advanced EDA tools, both performance and power have been optimized.