Research On Three Dimensional Memory Architecture In Multi-Core Processors

Multi-core architecture is the mainstream microprocessor design methodology, butit is facing the challenging Memory Wall problems. With the increasing number of coresandthreadsonchips,thebandwidthandperformanceofthememoryhavebecomethebot-tleneck.The three dimensional integrated circuits (3D IC) technology is a new integratedprocess, which can connect many dies with TSVs to increase the on-chip silicon resourceand shorten wires to increase the on-chip memory resource and decrease the access timeto overcome the barrier.Based on this technology, the memory logical structure, organization, circuits, inter-connect are presented and a thorough analysis of delay, energy consumption, area esti-mation methodologies of the on-chip memory are given. After summarizing the current3D cache designs and pointing the shortages of the 3DWL and 3DBL strategies, a newarchitecture called 3DSC is promoted, in which a less stringent TSV technology can beapplied. For the purpose of evaluation, a structure estimation tool, 3D SCACTI, based on3D CACTI, is used to contrast the three strategies. The experiment results show that ina 25nm 8MB cache case, 3DSC doesn't worsen the performance and expands the designspace.According to the problem of poor technology and model precision in 3D CACTI,a new tool 3D CACTI5 is built on CACTI5 to evaluate the delay, energy, area of 3Dmemory structure. With the help of 3D CACTI5, different 3D structures are compared toanalyze their delay behaviors. The interconnect parts whose performance has increasedmost are also found. A new energy consumption criteria is given to contrast the energyconsumption behaviors of different 3D structures. The experiment results show that 3DIC decreases the static energy consumption but worsens the static one, and it also canintegrate LSTP, LOP instead of HP to achieve both performance and low power goals,and has the potential to lower the projection of the wire engineering. With 3D CACTI5,a 3D cache can be chosen to meet the design goal.In conclusion, this thesis analyzes the 3D on-chip memory architecture thoroughlyand establishes the 3D memory estimation tool.