Design And Implementation Of Isomrphism Multi-core Processors Based On NiosⅡ With Fpga

Integrating multiple processors on the single chip to improve the SoC (System on Chip) performance has been becoming a trend. And the leading challenge is the communication architecture.Traditional design of SoC was based on the single-layer bus, but with the increment of IP(Intellectual Property), the efficiency of communication between them is becoming a bottleneck and, worsen the whole system. In the paper, a design of MPSoC (Multiprocessor System-on-chip) based on IP multiplexing is brought forward. And a kind of hierarchical bus based architecture is proposed in the MPSoC. MPSoC has a two-layer bus, and the communication between processors and local-memory through the local bus. The visiting of processor to sharing module is by whole bus. Two buses were linked by bus-bridge. The chip consists of four local processor subsystems and sharing module (shared memory, interrupt controller, resource management) components. Each processor subsystem with the same structure, include the processor core and local memory. Processors run task with master-slave mode and can also be used independently to run parallel tasks. The shared modules were managed by resource management, thus solving the conflicts of visiting sharing modules. A kind of interrupt mechanism was designed in this paper, which further improving the efficiency of communications between processors.The design is programmed with VHDL, and the two bus and the functional modules were simulated with EP2S130. Compared with similar chips, the MP SoC, since its layer structure and unique operational mechanism, has a parallel and multi-tasking feature. It has higher efficiency of communication and the real-time response to external events.