Research On Design And Implementation Technology Of Embedded Multiprocessor

The range of embedded applications has been extended to compute-intensive applications from industry control domain, and it requires high-performance embedded microprocessor. With the rap-id development of very large scale integration technology, the advanced multi-core architecture has been prevalent approach to further improve the processor performance and meet the increasing magnitude of application requirement, instead of high frequency. Recently, with the promotion of integrate circuit conditions, multiprocessor has come into sight. However, there still remain lots of problems to be solved. Therefore, it has great theoretical and practical significance to deeply study on the design and implementation techniques of embedded multiprocessor.Synthetic Aperture Radar real time imaging is a typical compute-intensive embedded applica-tion. It is widely used in fields of military, economy and environment. Taking the real time SAR imaging as a practical example, this thesis focused on solving on the problem of the design and im-plementation techniques of embedded multiprocessor, which is used for high-performance compu-ting. Aim at the high computing power demand of embedded application, a processor architecture model base on "task cluster" has been proposed, and on the basis of the model, we designed the embedded multiprocessor architecture. This thesis also proposed double-layer hybrid multi-core communication architecture, by studying the relationship between communication feature of appli-cation and communication performance of monolayer and hierarchical NoC, and discussed the se-lection and architecture design of router. FFT is the major computing task of SAR. To accelerate the FFT calculation, the thesis proposed a parallel FFT processing architecture. Finally, base on these research works, we developed a real time SAR imaging prototype system.Primary innovative works of this thesis can be summarized as follows:1. We proposed a processor architecture model base on "task cluster", and on the basis of the model, designed the embedded multiprocessor architecture. Aim at the high computing power demand of embedded application, the architecture model base on "task cluster" improved the com-puting power of processor by accelerating regular computing task. We also studied the relationship between communication feature of application and communication performance of monolayer and hierarchical NoC, and proposed double-layer hybrid multi-core communication architecture.2. We simulated and analyzed the communication power of two different NoC, which re-spectively Integrate circuit-switched routers and virtual-channel packet-switched routers, under dif- ferent communication feature. Circuit-switched router sets up the link form source to destination in advance, so the flits continuously and sequentially arrive. the area of router is small. The commu-nication power is acceptable when packet length is a few hundreds, but when a few dozens, cir-cuit-switched router has poor performance. Virtual-channel packet-switched router cannot guaran-tee continuous arriving of the flits, and the area is much bigger than circuit-switched router. But the router shows good communication performance, no matter the packet length is long or short. Ac-cording to the above conclusions, we can select suitable router in the design process of NoC.3. We proposed a circuit-switched routers supporting virtual-circuit. The experiments showed the innovative router can provide throughput increase and latency decrease, compared with basic circuit-switched router.4. We proposed parallel Radix-2×K FFT processing architecture, which can achieve con-flict-free parallel memory access. According to the conflict-free memory access algorithm, K2-radix butterfly can realize parallel accessing2K operands, and the processing speed of FFT was improved K times. Compare with other parallel FFT architecture, the parallel address produce module of the innovative architecture is uniform, so the architecture has good scalability.5. We proposed an application mapping algorithm and an interconnection communication solution, aim at multi-core chipset. Bandwidth of interconnect bus in the board is low. And restrict-ed by the pin number, the number of data path is small. Experiments show with the application mapping algorithm, we can effectively reduce the traffic between chips, and prove system perfor-mance. Meanwhile, interconnection communication solution solved the problem of the packet transfer between different multi-core chips. And this solution is not restricted by the chip number, topology and routing algorithm.6. We designed and implemented a real time SAR imaging prototype system. It mainly in-tegrates4Xilinx Virtex-6-550T FPGAs and several other chips. The design of4FPGAs all adopted embedded multi-core architecture. The prototype system pipelined computed SAR raw data, and acquired a256level gray SAR image which contained4096×2048points in18seconds at the speed of85MHz. It has little distinction between the acquired image and original image by means of PC.