FPGA Prototype Design For Multi-Processor System-on-Chip Of Six Processors

In recent years, using MPSoC instead of a single processor SoC gives prominence to its parallel deployment. There are four technology development directions to improve system performance: improving the efficiency of the implementation framework, multiple processors design, scalable design, deep-level functional integration. And the major challenge is how to improve the extensibility of the Multi-Processor System-on-Chip. The scalable means not only the number of processors, but also system-on-chip can be achieved close to linear speedup. Scalable design is not only a technical but also a design principle.Based on the hierarchy bus structure environment, we design The MPSoC platform of six processors and research on scalable resources, as well as Multi-Processor communication bus to the expansion of independence. Hierarchy bus structure includes local communications subsystem level and the global communication level. Local bus communication subsystem level is responsible for the communications between processor and local memory. The global communication level is responsible for the communications between processor and share memory.This dissertation was supported by the following projects:The project of "Basic Research of Networks-on-Chip Architecture and the Design Methodology" supported by the National Natural Science Foundation of China (No:60576034);The project of "Research of On-Chip-Network Key Technology of Networks-On-Chip" supported by the Specialized Research Fund for the Doctoral Program of Higher Education (No:20050359003);The project of "Basic Research of Embedded MPSoC" supported by the Natural Science Foundation of Anhui Province (No:070412031).The main work and achievement were as follows:1. The MPSoC platform of six processors was implemented at RTL, describing the scalable design of On-chip Communication Architecture based on hierarchy bus. We verified the whole system, some waveforms were presented here. From the results of verification we can see that the expansion of communication architecture met the requirement of MPSoC platform. When the system has multiple processors in the framework, various processors can communicate with the bus, so as to achieve the task of efficient collaboration.2. Prototyping the whole system based on Stratix II EP2S180 FPGA development board. We write a pipelined-matrix-multiplication program using ARM assembled language and co-simulation with the whole system. The whole system including hardware and software fits on the single FPGA. Experimental results had been obtained running at 60MHz with total area requiring 52% Adaptive Look-up Tables (ALUTs) and 24% on-chip memory of Altera Stratix II EP2S180.3. The result of experiment shows that with the increment of workloads, the speedup of six processors came up to 5.5. The result shows that the speedup is also growing with the increase in the number of processors. That is to say the cost of the communication between multiprocessors is diminishing. The speedup of four processors came up to 3.7, Total area requires 34% Adaptive Look-up Tables (ALUTs). From this we can draw the following conclusions: Researching on Hierarchy Bus based FPGA prototype for MPSoC, the percentage of performance enhancement and area increase are in direct proportion to the number of processors. So that we can upgrade the whole system prototype chip performance by increasing the number of processors.