Research And Implementation Of Multi-core Processor Based On NoC

With the development of the integrated circuit manufacturing process, it is difficultto further improve the performance of single-core processor.More and more attentionhas been paid to multi-core processor.The System on a Programmable Chip（SOPC）based on FPGA has flexible design approach，which can provide a faster and moreeffective way to design and implement multi-core processor.After thoroughly investigating the latest design method of Xilinx SOPC, aextensible multi-core processor platform based on Microblaze soft core processor isdesigned and implemented on FPGA.The multi-core processor platform design includesinter-core communication design and processor node design. Network on Chip (NoC) isadopted for inter-core communication. Compared with the traditional SoC bus, the NoChas many advantages such as wide communication bandwidth, strong expansibility andsupporting design reuse etc. The thesis selects2D-mesh topology, packet-switchingalgorithm and deterministic routing as the NoC design. This scheme not only consumesless resource and has smaller data transmission delay but also doesn’t cause deadlockissue. For the processor node part, the thesis has researched and designed the scheme forthe processor node including the main control unit and the configurable interface unit.The main control unit is based on the Microblaze, and it configures devices includingthe memory, AXI bus, DMA and so on, and it is mainly used for processor node controland simple data processing.To further improve the performance of the processor, theconfigurable interface unit provides a universal interface for the accelerator.For the multi-core processor platform scheme, the thesis divides it into four partsto design them respectively. In the main control unit part, it gives the characteristics,parameter settings and connections for each IP core. In the interconnection interface part,it gives the specification for the generation of IPIF and the usage of interface signal. Inother two parts, it gives the corresponding design ideas and hardware structure. In orderto make it convenient for the main control unit to control the configurable interface unitdirectly, the processor node module gives the hardware structure for instructiondecoding and instruction collection. At last, according to hardware structure designed in the thesis, a2*2mesh scaleNoC4-core processor platform is implemented on Xilinx’s Virtex-7series FPGA chipXC7VX485. The thesis has completed the software design of the multi-core processorplatform, including initialization of the system and the typical standard IP core softwaredesign. And it gives evaluation to the multi-core processor platform’s performance byusing a large matrix multiplying. The evaluation results show that the processorplatform not only can function correctly but also can provide a faster speed which is286.73times of a single Microblaze’s speed.