Study On Evolvable Circuit Of Convolution Codes Based On Reconfigurable FPGA

The study of reconfigurable FPGA belonged to the field of evolvable hardware, and it's an idiographic method to realize EHW. The purpose of channel coding is to improve the dependence of communication. Convolution coder and Viterbi decoder are one of channel coding. And convolution code is used in the operation which requires more real-time during 3G mobile communication system.Noticed convolution code is a practical project to realize core-base dynamic reconfigurable FPGA circuits which are fit in this study. A model of programmable logic tree based on FPGA was use as the base core of reconfigurable FPGA named T_A, then an element T_B was made based on T_A, T_B can realize all functions of error-correct circuits by reprogram it's control line .Using T_B to format' FPGA before circuit was programmed, so it is regularly to lay out on the FPGA. This kind of structure could be reconfigured by register storing data stream. In theory, basic principles and the evolutionary algorithms of the EHW were briefly introduced firstly, then the fundamental modularize methodology of core-based dynamic reconfigurable FPGA was described, and later a kind of hardware nesting GA was forward. At last, using VHDL according to nesting GA with RLA FSM as a controller of dynamic error correcting code reconfigurable circuit.In experiment, the VHDL language and schematic describe are used to design the cyclic error-correcting code circuits on core-based dynamic reconfigurable elements, A detailed Convolution error correcting code circuit was carried out and the function simulation upon Xilinx Foundation FPGA system was done, and then be implemented on a chip of Virtex-E serial FPGA.