The Research Of The Implement Of Evolvable Hardware Using The SOC Design Flow On A FPGA

Evolvable hardware (EHW) is a new field based on the evolutionary algorithms (EA) to create circuits. It is comprised of reconfigurable hardware, artificial intelligence, fault tolerance and autonomous systems. Evolvable hardware refers to the hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. With these characteristics, the Evolvable Hardware not only can realize the automatic design of complex circuits, optimize circuit structure, but also achieve self-repair function in an effective way.EHW can be merged as the integration of evolutionary algorithms and the programmable devices; as a result the study of implementation EHW should include the algorithm realization as well as the configuration of programmable devices. This thesis focuses on the research of these parts, and implements them using the SOC design method on a FPGA.Firstly, the concept of EHW is introduced in this thesis, as well as some classifications and descriptions. Then an overview of the genetic algorithms and the structure of the reconfigurable FPGA are given. On these bases a FPGA-based SOC EHW design using of the ISE and the EDK develop kit software is made. Finally, the internal logic function is validated by Chipscope, at the same time the related data is also analyzed. The result shows that the FPGA-based SOC design method of EHW implement accomplishes the purpose desired, is feasible and obtains the value of research.