Research And Implementation Of Key Techniques Of High Performance Floating-Point Unit Designs

Since the recent 60 years,there has been a rapid progress in the microelectronics and integrated circuits. Under the circumstance, microprocessors have amazing development and the performance has been improved rapidly. At the same time, in order to meet the requirements of high-performance, floating-point processing unit (FPU), the critical unit, must have fast speed .Some of the existing floating-point processing unit basically achieved good performance, but there are still some problems. In the FPU, the floating point multiplication algorithm started moving towards a higher band, greater interface and higher degree of parallel. The speed and area of Multiplier directly impacts on the performance of FPU, so the multiplier design need to be improved and optimized.FPU in the division and square root is still computing the performance bottleneck, whose structure is more complex and also has large area and quite big power.To address the problem, this paper studies the key technologies of FPU. Against the 64-bit multiplication we propose Pseudo-1 transformation strategy in the partial product generation circuit, which optimize control pathway. Meanwhile, in the traditional Wallace tree multiplier we propose the pseudo-plus approach , which not only reduces the delay, but also reduces the complexity of the circuit. On the basis of floating point multiplier realization, this paper implements the design of floating-point division using the Goldschmidt and look-up table method. We implement a FPU with order execution and chaotic sequence outflow. The design takes full advantage of the FPU resources and improves the performance. With all these design technologies this paper designes and implementes a high-performance FPU. And with the analysis and testing, we prove the design techniques and the effectiveness of correctness.First, floating point adder, the key parts, is analyzed in this paper. On the basis of the In dual-channel (Two-Path) structure, this paper studies the normalize process of floating-point adder . Then we put forward solutions to the problem using leading zero detection algorithm. The design shorteres delays and simplifies the circuit design.Secondly, against the 64-bit multiplication, we set optimal control pathway in the partial product generation circuit and proposed Pseudo-1 transformation strategy to reduce delays, simplify the circuit design and reduce the size and power consumption.At the same time, in the traditional Wallace tree multiplier, we introduce the carry-Prefetching and low-Round Strategy in the process of compression array. This paper proposes the pseudo-plus approach,which not only reduces the delay, but also reduces the complexity of the circuit. Combining pipeline design technology, this design can complete a single or double-precision floating-point precision multiplication.It meets the rapid calculation of 3-D graphics and high performance requirements of FPU.Fourthly, on the realization basis of floating point multiplication ,this paper implements the design of floating-point division using the Goldschmidt and look-up table method. Fifthly, based on the above realization of the key components, we implement a FPU with order execution and chaotic sequence outflow. The design takes full advantage of the FPU resources and improves the performance.Finally, after studying key technologies, this paper designs and implements a high-performance FPU, which realizes the various technologies presented in the paper. Through testing and simulation, test results show that the FPU satisfies the requirements of performance, power and area.