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Keyword [BOOTH Algorithm]
Result: 1 - 20 | Page: 1 of 2
1.
Design And Simulation Of FIR Digital Filter Using FPGA/CPLD
2.
The Design And Optimization Of The Saturating MAC Unit
3.
Design And Implementation Of A Fixed-Point Arithmetic Unit
4.
Study And Design Of Floating-point 32 Bit Parallel Multiplier
5.
Research And Design On High Performance And Special Arithmetic Unit Based On FPGA
6.
Design Of High Speed Multiplier
7.
Research And Application Of ASIC Design
8.
Design Of The FFT Processor Based On All-Digital OFDM Receiver
9.
Research And Implementation Of Key Techniques Of High Performance Floating-Point Unit Designs
10.
Design Of A Four Stages Pipeline Digital Signal Processing Core
11.
A Design Of High-Performance Multiplier
12.
Design And Implementation Of The Low-Power DSP Multiply-Add-Fused Unit
13.
Crucial Technology Research On High Performance Parallel Multiplier
14.
The Design And Verification Of A YHFT-DX+ Multiplier Unit
15.
The Design And Verification Of An 18-bit Configurable Multiplier Which Based On Modified Booth Algorithm
16.
The Design Of Low-Power Multipliers Based On Booth Algorithm
17.
Design Of Multiplier IP Core For DSP
18.
Research And Design Of54b×54b Redundant Binary Multiplier
19.
Reliability Research Of Booth Multiplier Based On Formal Methods
20.
The Design And Verification Of Multiplier Applied To The Powerpc Processor
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