High-performance Floating-Point Unit Design

Many numerically intensive applications, such as real time signal processing, require rapid execution of arithmetic operations for floating-point numbers. The computational demand goes beyond fast floating-point addition and multiplication. Support for high-performance floating-point divide and multiply-add fused is becoming increasingly necessary. These proposed arithmetic units are substantials of a FPU. We proposed and analyzed the architectures of three floating-point arithmetic units: floating-point adder, multiply-adder fused and divider. The proposed floating-point adder supports denormalized number by adding a decoder and some simply logic unit. This modified double-precision floating-point adder combine some optimization techniques such as: a non-standard separation into two paths, partial compression and recoding to implement the LZA , sign-magnitude computation of a difference based on one's complement subtraction to reduce the recomplementation We propose an architecture for computation of the double-precision multiply-add fused operation A + ( B × C). This architecture is based on the combination of LZA and normalization. The proposed divider provides rapid convergence based on higher-order series expansion techniques. And a Booth multiplier accepting redundant input is used to reduce the latency.