A Design Of High-Performance Multiplier

A lot of multiplication need to be used in the process of digital signal. As an important component of digital signal processor, the speed of multiplier determines the performance of it directly. The frequency in the use of multiplication of floating-point takes a great amount in the operation of floating-point. The floating standard of IEEE754-1985 is widely used. The 43-bits floating-point multiplier was designed and suited for this standard in full custom. Firstly, the expression of binary system and the floating-point number of IEEE was introduced. Then, several general algorithms and circuits of the generation of partial product , the 4:2 compressor that was used to the compression of partial product, and several typical architectures that is used to compress the partial product, and multiple-bits adders and multipliers in common use were described. After that, the multiplier architecture of mine was proposed. A 30-transistors encoder and the circuit of the generation of partial product with translation gate, and a compression architecture between Wallace tree and iterative array was designed. The 4:2 compressor was optimized in transistor level, a novel 60-bits high speed carry propagation adder was proposed, a 64-bits static shifter was constructed, which made the position of the round of mantissa definitely. Besides, a advanced scheme of the summation, adjustment of exponent and the normalization, round of mantissa was designed, 4 modes of round were supported, so various signals can be computed simultaneously, which made the speed of this part high. About 4705 gates were used for this multiplier. Functional simulation was executed with the tool of Verilog_XL on the platform of Cadence Virtuso, then its function was verified and the delay was 27.5ns by Hsim simulation, which achieved the expected objective.