The Development Of A 32-Bit Floating-Point FFT IP Core Based On FPGA

As the basic operations of the transform between time field and frequency field, FFT has been widely used in such fields as detection, communication, image processing, multimedia etc. The research of the implementation of the floating-point FFT algorithms on FPGA is becoming the new research hot spots, which has been paid high attention to.In the thesis, on the basis of the analysis of the main kinds of FFT algorithms and hardware architectures which can be used to implement FFT processor, the decimation-in-time radix-2 algorithm is chosen as the target algorithm, and the architecture of single-butterfly-sequential-processing is utilized to implement the design in detail. Then the description of the design of the hardware architecture of the floating-point multiplier and the floating-point adder is made, in which several novel techniques are adopted such as high-speed fixing-point multiplier, fast leading-0-detector-logic and pipeline etc. Based on this, the design of the whole architecture of the FFT is detailed, in which the modified butterfly-unit, memory unit, address generation unit etc are included.A hardware test and analysis are performed on the FPGA hardware test platform. The test shows that both the operation precision and speed are high, and the system can steadily run at the frequency of 50MHz, and the processor can finish the FFT operation of a frame of 256-point floating-point complex data within 81.92μs. It shows an advantage to the universal DSP and MCU.