The Design And Simulation Of 3D On-chip Optical Interconection System

With the increasing integration level and complexity of future System on Chip (SoC), traditional on-chip communication architectures based on bus cannot adapt to current design requirements. The emergence of Network on Chip (NoC) provides a new solution for future MPSoCs. With the further development of technology, traditional electrical NoC are exposing various disadvantages such as limited bandwidth, long delay, high power consumption and so on. Optical interconnect technology has extremely high communication bandwidth and minimal transmission losses, which makes it an ideal technology for on-chip interconnect, and optical Network on Chip (ONoC) has become a research hot spot in recent years. Compared with traditional two-dimensional design, 3D integration technology has higher packing density, reduced wire length and lower power consumption. Therefore, the ONoC combining with 3D integration technology will have great potential in the future high-performance chip design. We firstly established the 3D Mesh ONoC simulation platform in OPNET, and made a performance analysis of this architecture from ETE delay, throughput, area, and power consumption; then we proposed two new 3D ONoC structures, designed new router architectures, routing algorithms and so on, and we also made a performance evaluation of new structures, the results show that these two new 3D ONoC structures have certain comparative advantages in terms of network performance and cost overhead.