Energy-efficient Design Techniques For Network-on-Chip Based Multiprocessor Systems-on-Chip

SoCs(System-on-Chips) have been widely applied in embedded electronic devicesfor communication,signal processing and multimedia.Since uniprocessor SoC couldnot satisfy the growing computation requirements of such applications,MPSoC(Multiprocessor SoC) platforms have emerged for high performance embedded systems.With the rapid development of IC technologies,there will be billions of transistors andhundreds of heterogeneous IP cores on a single chip.Due to poor scalability,communiction perfomance and energy efficiency,bus will not suite for MPSoCs,so theinterconnect subsystem will be the bottleneck of such complex MPSoCs.As a newparadigm,NoCs(Network-on-Chips) have been proposed to overcome the complexon-chip multi-core communication problems,providing opportunity and challenges todesign methodology of embedded systems.For the sake of extending the lifetime ofbatteries,reducing the cost of package and cooling,and improving reliability,energyefficiency have been the most important factor of NoC-based MPSoCs.In this dissertation the design methodology of embedded systems is summarized,and the design methods of NoCs are analyzed.Then a novel system-level design flowfor energy efficient and NoC-based MPSoCs is presented.More precisely,in thefollowing chapters,4 key design problems are identified and solved for embeddedapplications with low cost,hard real-time,high performance and high dependabilityrequirements.These problems include:(1) hardware-software partitioning of MPSoCcomputation platform,(2) IP mapping of firm NoC platform,(3) routing path allocationand links voltage assignment of hard NoC platform,(4) hardware-software co-synthesisof soft NoC platforms.In this dissertation,the main works and contributions are as follows:(1) A hardware-software partitioning algorithm using Autowave CompetitionNeural Networks is proposed for MPSoCs based on reusable components.Thepartitioning problem is formulated as a multi-constrained shortest path problem.Theautowaves are designed specially to solve the shortest problems optimally.Finally,eachtask module of the system is allocated a software component or IP core from the components library,such that the power consumption of the MPSoC is minimizedsubject to cost and timing constraints.This algorithm could obtain globally optimalsolutions,and it's parallel and non-parameter.It's easy to implement the neural networkby VLSI.(2) An improved Tabu Search algorithm,called TSNM,is proposed for low-energymapping problem of 2-D Mesh NoCs subject to communication latency constraints.Based on"intensification and diversification"mechanism,TSNM merges Robust TabuSearch and COHX crossover operator.Experimental results show that TSNM can givebetter quality solutions and smaller searching space,so it is more efficient to solvelarge-scale NoC mapping problems.(3) A recursive bipartitioning algorithm,called RPM,is proposed for low-energymapping problem of tree based NoCs subject to communication latency constraints.RPM is an efficient divide-and-conquer approach and calls modified Kemighan-Linheuristic to perform mincut partintioning of IP core communication task graphs.Experimental results show that RPM obtains lower energy mapping solutions and it isvery fast.It is suited to both producing excellent results and quick NoC design spaceexploration by tuning the parameter of RPM.(4) A reliability-aware energy optimization algorithm is proposed for NoC withvoltage scalable links.Considering the effect of reduced voltage on fault rates,thisapproach achieves energy/reliability trade-off when performing routing path allocationand links voltage assignment.A novel energy-efficiency gradient driven heuristic isdeveloped to assign the voltages for the links during Tabu Search based global designspace exploration of routing path allocation.Experimental results show that thepresented method can efficiently guarantee the communication reliability andbandwidth constraints,and obtain significant energy savings of communication links.(5) A hardware-software co-synthesis algorithm is proposed for voltage islandsbased hierarchical NoC systems.A novel design framework based on iterated GeneticAlgorithm is developed for the complete co-synthesis flow of dependable embeddedreal-time MPSoC applications.The multi-objective optimization techniqueautomatically performs resource allocation,task assignment,cluster mapping,taskscheduling and voltage assignment to trade-off energy and reliability of NoC systems.Experimental results show that the proposed design technique performs significantly better than existing algorithms in both energy minimization and reliability.It is suitedfor system-level synthesis of heterogeneous hierarchical NoCs.At present,the researches on MPSoC/NoC design methodology are in the stage ofinitial development,and there are many open problems left.The design methods andenergy optimization algorithms presented in this dissertation may provide some newtechniques and ideas to design automation of next-generation embedded multi-coresystems based on NoC.