Design and integration of current-mode on-chip interconnect signaling in nanometer technologies

As feature sizes progress into nanometer realms, on-chip interconnects play an increasing role in the overall performance and power consumption of high-performance integrated circuits. Three novel on-chip interconnect communication techniques are presented; (i) differential current-transfer sensing, (ii) multi-level current signaling, (iii) swing-limited interconnect communication; silicon implementation and an integration methodology in conventional CAD flow are proposed. The differential current-transfer sense amplifier ( DCTSA), is a new static-power mitigated receiver for conventional differential current-sensing. It is compared with the conventional differential current sense amplifier (DCSA) and standard repeaters. Results in 130nm, 65nm and 45nm show that DCTSA outperforms repeaters for wires with activity of 50% and higher and length longer than 4mm. The multi-level current signaling technique with novel driver and receiver circuits is proposed which encode two bits on one interconnect using current levels. This multi-level system is compared with conventional repeaters for process technologies including 130nm, 90nm, 65nm and 45nm. The impact of process induced parameter variations was analyzed and a process tolerant driver was presented. Compared to repeaters, multi-level current signaling is attractive for wires longer than 4mm and with activity factors more than 40%. A swing-limited interconnect current-mode technique is proposed with a novel low-swing receiver circuit, which achieves energy efficient transmission for on-chip interconnects over repeaters. This swing-limited interconnect system is compared with repeaters in a 65nm industrial CMOS technology. With this signaling technique there is a 56% energy reduction and 21% delay reduction compared to repeaters. Delay savings increase by 8% at supply of 1.4v at iso energy. A total area savings of 86% is obtained in device width with this technique. A methodology and tool for the integration of current-mode interconnect techniques into conventional design flow was presented. The methodology and tool called Network-on-Chip Interconnect Calculator provides results in terms of delay and power for interconnects, and illustrates the effects of delay and power on input parameters in plots. It hides the circuit level details of the proposed current-mode techniques and provides a simple library that can be used by conventional CAD flow. The proposed signaling techniques along with conventional repeater insertion method have been implemented in silicon in IBM 130nm technology through MOSIS for different wirelengths showing proof-of-concept. The test chip is fully functional and the measurement results closely followed the simulated results, thus verifying the validity of the proposed techniques and their benefit over existing techniques for on-chip interconnects.