Current-mode band-limited signaling for global on-chip interconnects

Global on-chip interconnects are a limiting factor in modern high performance VLSI systems due to cross-talk noise, signal delay and wire bandwidth constraints. This dissertation addresses these limitations with a fundamental change in signaling technique—the use of current-mode band-limited pulses. This work is intended to establish the theoretical basis for the proposed signaling scheme while formulating its impact on signal delay, bandwidth and cross-talk noise both analytically and experimentally. Simple yet accurate closed-form delay and power dissipation expressions for inverter driven on-chip interconnects with arbitrary receive-end termination are presented. The solutions can be used for both resistive and capacitive termination to adequately model current and voltage mode sensing used in repeaters for interconnect signaling schemes. The performance of band-limited pulse signaling for cross-talk noise reduction in high-density on-chip interconnects is addressed using reduced edge-rate pulses. A comparative analysis is presented to evaluate performance in cross-talk noise, driver/receiver power dissipation and propagation delay. Test chips fabricated in AMI 1.6μm bulk CMOS technology are used to experimentally evaluate the performance of the proposed techniques.; This dissertation also explores a novel on-chip adaptive bandwidth bus (ABB) designed to automatically increase or decrease the interconnection bandwidth to track the input data activity envelope, thereby minimizing the static power dissipation associated with low impedance current sensing without a penalty in maximum attainable data rate. To demonstrate the feasibility of the proposed bus, “analog” and “digital” implementations are fabricated in AMI 1.6μm and TSMC 0.35μm CMOS technologies, respectively. In addition, a power dissipation modeling approach based on circuit-level and statistical analysis of microprocessor data streams is presented to evaluate the performance of the proposed bus. Attaining a maximum aggregate bandwidth of 16Gb/s (i.e. 1Gb/s per line) across lossy on-chip interconnects spanning 1.75cm in length, the digital bus core dissipates approximately 93mW with a supply of 2.5V and signal activity of 0.5. Experimental results indicate a reduction in power of 50% over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%–70% and 66% over voltage-mode (VM) sensing, respectively.