Research On High-speed And Low-power On-chip Interconnect Circuit

In the era of multi-core and nanometer technology,chip area dose not shrink with the technology scaling,so interconnect wires which connect the function blocks as clock,address or data buses remain about the same length.While the wire width is becoming smaller,the RC delay actually increases.In order to reduce the delay,designers normally have to increase power consumption.Therefore,long wires are critical for the speed and power performance of the chips.Even with 2.5D and 3D technologies,long global interconnect wires are still necessary for horizontal interconnect.This dissertation focuses on the study of the circuit design of on-chip long interconnect,targeting both low power and high speed.This dissertation firstly reviewed the existing solutions for long distance on-chip interconnect.It shows that AC coupling and current mode wires are two main schemes for high speed and low power interconnect.In order to explore the delay performance of these two schemes,this dissertation carries out delay analysis based on the Asymptotic Waveform Evaluation(AWE).New delay calculation metrics are proposed for these two wires respectively.It has been found out that the propagation delay of the capacitive coupling or current mode wire is about one third of conventional wire.In addition,the new delay metrics demonstrate that optimal designs can be obtained in RC limited long on-chip wires by adjusting the location of the coupling capacitor or resister to ground in the two wires.The delay of the wires can be reduced by 30% in optimal designs.To further analyze the capacitive coupling or current mode wires,ABCD matrix based method is applied to explore the influence of inductance parameter.An energy dissipation model for capacitive coupling wire is also proposed.Energy and delay performance is evaluated based on this new energy dissipation model.A double capacitive coupling and capacitive-resistively driven wire is also proposed to improve the energy and delay performance.SPICE and electromagnetic simulation environments are established,and the delay metrics and optimization methodology are verified by simulations.In order to verify the proposed design optimization method,a test chip has been designed and taped out in SMIC 130 nm Mixed Signal technology.Different capacitive coupling wires with 10 mm length have been implemented in the test chip.The measurement results verified that the proposed design optimization methodology can improve the 3dB bandwidth of the capacitive coupling wire by about 50%.A transceiver circuit has also been implemented in TSMC 90 nm low-K CMOS technology by using the optimized capacitive coupling 10 mm wire.Compared to the reference design,bit rate can be improved by 25% and the energy consumption can be reduced by 19.96%.The measurement and simulation results demonstrated that the proposed optimal design methods can effectively improve the performance of long distance on-chip interconnect.