On-chip signaling techniques for nanometer VLSI designs

The continued increase in performance and integration levels of VLSI designs for the last three decades has been fueled by shrinking transistor sizes. Unlike devices, on-chip wires get slower with technology scaling and pose performance and power challenges as VLSI designs scale into the nanometer regime. At the same time signal integrity issues have also become important due to increased cross-talk and inductive effects and pose reliability challenges for on-chip signaling. This thesis proposes on-chip signaling techniques to provide higher performance, lower power or improved robustness beyond those achievable by current design solutions.; Active shielding is shown to improve wire performance and/or robustness. Unlike traditional shielding approaches, active shielding involves switching the shield wires along with the signal wire to improve performance through the dominant coupling (capacitive or inductive) between them. Delay gains of up to 10% are achieved for RC wires while up to 40% improvement in transition times and 4.5X reduction in overshoots are achieved for inductive wires.; Energy reduction is achieved by reducing one or more of the dynamic power components (capacitance, switching activity or supply voltage) with minimal performance penalty. The Transition-Aware Global Signaling (TAGS) receiver reduces total switched capacitance by reducing the number of required repeaters for a fixed wire delay. The lower repeater count is achieved by the ability of the TAGS receiver to detect transitions at the end of a wire much earlier than a standard inverter receiver. Energy gains of up to 50% are achieved with a TAGS bus operating at 1.5GHz. Various bus encoding circuits and techniques are also proposed to minimize on-chip bus switching activity with minimal impact on performance. The design space where the various encoding techniques are preferable is also analyzed and shown to achieve peak energy and current reductions of up to 32% and 65%, respectively.; Repeater and bus design techniques are proposed that allow more energy efficient signaling in dual-VDD systems than the standard approaches. Increased energy efficiency is achieved by improving performance (up to 22%) with lower supply signaling while consuming less energy than signaling at the higher supply. On-chip buses are typically designed to operate correctly at a fixed frequency and voltage supply under worst-case conditions. For typical operating conditions, the bus is faster than it needs to be. A Dynamic Voltage Scaling (DVS) technique is proposed for on-chip buses to aggressively scale the supply voltage to the point where the bus just operates correctly for the actual operating conditions on the chip, thereby achieving significant (up to 39%) energy gains with minimal (less than 2%) impact on performance.