Research On The Design And Implementation Techniques Of Customizing Application Specific Instruction Set Processors

In recent years, the markets for PDAs, cellular phones, digital cameras, network routers and other high-performance but special-purpose devices has grown explosively. In these systems, embedded processors must meet the challenging cost, performance, and power demands. General purpose processors (GPPs), although inexpensive, may fail to meet performance and power cost demands of these embedded applications. To address this problem, the recent popular solution is customizing a number of special hardware computation functional units, viz. computation accelerators, coupled with a low cost GPP core. The instruction set extensions which are supported by these computation accelerators are used to accelerate those applications to meet their performance demands. These processors coupled with customized computation accelerators are called application specific instruction set processors (ASIPs).Compared with designing application specific integrated circuits (ASICs), the design of ASIPs needs fewer modifications on the original processor core, which can greatly shorten processor design time. Automating the design process of ASIP can enhance its time-to-market advantage over ASIC. This dissertation mainly focuses on the important techniques of customizing ASIPs, including automatic instruction set extension, optimal computation accelerator customization for multi-issue ASIP, computation accelerator virtualization for ASIP, and a case study of multi-core ASIP customization. These techniques and design choices are comprehensively explored in this dissertation, and are demonstrated effectiveness by the results of experiments.This dissertation makes the following contributions:1. A fully automatic instruction set extending workflow for ASIP is proposed, which was implemented on the transport triggered architecture (TTA). This approach can automatically extend the instruction set for given applications, and estimate speed up and area consumption for instruction patterns. Experimental results show great performance improvement on various embedded applications under given hardware constraints.2. An optimal computation accelerator customization methodology for multi-issue ASIP is proposed. The performance of multi-issue processors are often restricted by the critical paths of data flow graphs. This dissertation proposes an optimal computation accelerator customization methodology targeting for minimizing critical paths. The experimental results show that the optimal methodology not only performs better than the greedy method, but is also time tractable.3. The computation accelerator virtualization technique is proposed. The computation accelerators in ASIPs can only accelerate the applications that are compiled with instruction set extensions. Those applications compiled without instruction set extensions can not benefit from the hardware accelerators at all. In this dissertation, we propose using software dynamic binary translation to overcome this problem, i.e. computation accelerator virtualization. Unlike a static approach, dynamically utilizing accelerator poses many new problems. This paper comprehensively explores the techniques and design choices for dynamic accelerator utilization, and demonstrates the effectiveness by the results of experiments.4. The customization method of multi-core ASIP is studied based on a case study of JPEG decoding. By a thourough analysis of JPEG decoding, the decoding process is divided into four sub processes, and instruction set extensions are customized for each of these sub processes. After this, the whole decoding process is further divided two main parts, and are paralleled in the pipeline way. Since JPEG decoding is one of the most common embedded applications, our work in this paper shows an example for a multi-core ASIP design.