Implementation Of GPS Synchronization Algorithm ASIP

As the main operation unit of GPS software receiver, signal synchronization arithmetic receives intermediate frequency input signal, and then obtains navigation data from it through dispreading and demodulation for following positioning unit. Signal synchronization arithmetic can be briefly divided into two phases, acquisition and tracking. Acquisition gains visible satellite number,cursory phase of the C/A code and cursory Doppler frequency shift of carrier by three-dimensional search; Tracking generates local signals which synchronized with input signals through adjusting the C/A code and Doppler frequency shift, so that C/A code and the carrier can be removed from input signals and the navigation data can be extracted. The correlators in the two phases are performance bottlenecks in implementing real-time GPS software receiver.As a trade-off between ASIC and general-purpose processor, Application Specific Instruction Set Processor (ASIP) possesses both specificity and flexibility. Signal synchronization algorithm of GPS is studied in this paper. According to its characteristics, ASIP of GPS signal synchronization algorithm based on Nios II embedded processor is implemented. At the same time, TRIPS with Explicitly Communication ISA architecture is proposed as another option of ASIP, and part of the signal synchronization algorithm is optimized through implementing with TRIPS assembly language based on its instruction set. At last, two ASIPs proposed are evaluated and compared, which explores the embedded real-time solution of ASIP-based GPS signal synchronization algorithm.Based on the analysis of acquisition and tracking algorithms, FFT/IFFT and Bit-Wise correlator are the key operation units of the GPS software receiver. This paper takes both of them as the main units to optimize, from which a set of specific instructions was extracted, and an exploration of Nios II-based instructions was made, then the ASIP is implemented in the Nios II IDE and verification was completed on a FPGA test-bed. Besides, TRIPS assembly optimization for FFT/IFFT and Bit-Wise correlator was made in order to achieve better performance. Finally, we extracted and analyzed performance parameters of the two realizations of ASIP, and compared them using normalized frequency. By analyzing performance parameters of the two ASIPs, we found that the ASIP based on Nios II had comparatively good performance, but TRIPS with Explicitly Communication ISA architecture put up better performance.