Study On Dynamic Instruction-Set Based Adaptive Processor

Application Specific Adaptive Processors (ASIPs) combine the flexibility and competitive time-to-market of embedded processors with the computational performance and energy-efficiency of dedicated VLSI hardware implementations. As they bring several advantages to different kinds of developers, they are becoming more and more popular. But the cost of developing ASIPs is large, especially for the time consuming of provision and verification of the tool chains. The problem of eliminating tool chain related cost poses a significant challenge.With the emergence of new technologies and varying user requirements, the requirements to processors become more and more challenging. ASIPs that designed with static instruction set are hard to meet all those requirements. So the research of brand new processor architecture is becoming more and more important.This dissertation presents the framework of an adaptive ASIP based on dynamic instruction-set to solve the problems. The adaptive ASIP mean to avoid the tool chain problems in ASIP development and to meet the varying user requirements. It intergrates reconfigurable technology with ASIP to support dynamic instruction set extension; it also keep the application binary interface unchanged during dynamic reconfiguration of hardware, in order to reuse the toolchain.This dissertation's key researches and contributions focus on follow aspects:(1) ASIP toolchain problem and its soultion: we analysis the typical ASIP design flow, point out the exsiting problems, and propose two solutions. First, we introduce an ADL-based verification methodology for co-verification of tools, instruction set specification and CPU model. Second, we describe the framework of Application Specific Adaptive Processor (ASAP) to avoid the toolchain problem and meet the varying user requirements.(2) Application characteristics and configurable profiler design: we first analysis the characteristics of application benchmarks, then design a configurable hardware profiler(CHP). CHP could work loosely with embedded processors, spot hot paths efficiently without too much hardware resources. We determine the crucial parameters with extensive experiments.Empirial experiments on path profiling show that the coverage of hot paths found by CHP are usually above 80%, providing great opptunities for instruction set optimization. (3) Instruction set extension and candidates selection algorithm: we first propose a custom instruction set extension algorithm for ASAP, including data flow analysis, instruction clustering, sub-graph enumerating and sub-graph merging. Experiments show that the algorithm could enmuerate all the non-trival candicates efficiently. Then we analysis the existing candidate selection algorithm and propose two new algorithms: as heuristic algorithms usually omit the difference between instruction and instruction instance, we improved one existing heuristic algorithm to GreedyHeur algorithm. It calculates custom instructions' weights from their instruction instances, then select custom instruction instances with greedy strategy according to their instructions' weights. To find better custom instruction than heuristic algorithms, we introduced an algorithm (ISDE) integrating greedy strategy with differential evolution algorithm. Simple encoding and efficient fitness evaluation help ISDE find the best combination of custom instructions quickly. Experiments show that our algorithms can find better custom instruction candidates more quickly and efficiently than heuristic algorithm.This dissertation also discusses about reconfigurable array architecture and dynamic techniques, and decribes a practical reconfigurable array architecture and its dynamic mapping mechanism based on hardware table.