0.2-10GHz Broadband Radio Frequency Access Front-end Circuit Design

Over the past few years,the ongoing advancements and breakthroughs in Io T chips have sparked a surge of interest in Io T devices,such as wearables and embedded medical detection devices.This trend has further stimulated the evolution of wireless communication technology.However,the progressively intricate and diverse network standards have resulted in more demanding requirements for the receiving bandwidth of RF receivers.As the most critical "gateway" in the wireless communication system,the front-end circuit of the RF receiver has a wideband performance index that directly affects the performance of the entire receiving link,so the research on the ultra-wideband RF receiver system is very important.Based on the RF 65 nm CMOS process,this thesis researches and designs an ultrawideband RF front-end circuit operating at 0.2-10 GHz,and uses Cadence Specter RF RF simulation software to design and simulate the low-noise amplifier and mixer and use the IQ RF receiver front-end system with two-way orthogonal structure.In order to make the overall circuit reach the target bandwidth and achieve the optimal level of bandwidth gain stability,the low noise amplifier of the RF receiver front-end system designed this time is based on the resistance parallel negative feedback structure and adds the input inductance peaking technology to improve the high frequency gain.The gain fluctuation within the design bandwidth is less than 0.7%,and the overall noise is reduced through multiple sets of power filter structures.In the mixer design,based on the experience-based Gilbert double-balanced structure,static current injection and inductance peaking techniques are used to obtain more stable voltage gain and lower noise performance.According to the simulation results of the RF receiver system designed in this question,at the foot of the TT process,the power supply voltage of 1V,within the design bandwidth of 0.2-10 GHz,the input matching is less than-10 d B,the noise figure is less than 7.2d B,and the noise corner 1/f is less than 100 M,The article will delve into the front-end circuit of the ultra-wideband RF receiver,covering its design process,pre-simulation,and post-simulation,as well as highlighting that the output1 d B compression point exceeds-5.2d B,while the maximum voltage conversion gain is approximately 30 d B.