Research And Design On Millimeter-wave Receiver Front-end Chip In 40nm CMOS

We are now at the dawn of a new era of wireless communication society.The Fifth generation mobile networks(5G)is the wireless standard that will address people's requirements.100x higher data rate is needed at 100x higher network efficiency and the service along with 5G requires lower latency and higher reliability.As the overcrowded spectrum at sub 10GHz is not a good choice for the new generation standard,millimeter-wave(mm-Wave)wireless communication is coming soon.CMOS is always the best choice for large-scaled digital circuits for its low expense.With the scaling of advanced CMOS process node,mm-Wave analog circuits find its way to integrated together with digital baseband leading to more and more portable devices.Thus,the CMOS process is a key technology for the future 5G mm-Wave communication and both industries and academia have payed a lot of attention in the last decades.In this work,we will focus on some challenges and propose some design techniques for wireless receiver in E-Band(71-86 GHz).According to theoretical calculation,the E-Band wireless communication system is supposed to achieve over 10 Gbps in several hundreds of meters in only one channel.By using multi-channel phase-array system and carrier aggregation techniques,it is expected to reach tens of gigabits per second which can be used in massive base station backhaul.A wide-band low noise amplifier(LNA)is proposed in this paper.With the limitation of cut-off frequency of MOSFETs,a multi-stage differential topology is used in the LNA design.By using wide band input-matching technique,the S₁₁ under-10dB is over 50GHz.The high-order inter-stage matching networks is based on coupled transformers.With the fine 3D-EM simulations,the LNA can achieve 20dB gain and4dB noise figure in E-Band.Futhermore,an E-Band receiver front-end(Rx FE)is proposed in the following work.Sliding-IF architecture is used in the E-Band receiver.The main work of this paper consists of wide-band LNA and double balanced passive mixer.It can achieve an average conversion gain of 19dB and the noise figure is at4.5dB.The input compression point(IP_1dB)is-19dBm and the input 3-order intermodulation points(IIP3)at100MHz offset is about-13.5dBm.Both the front-end chip and LNA chip is designed and fabricated in 40nm CMOS process.Some of these performances have been measured which is corresponded to simulation results.This work is supposed to be a technical support for further researches in mm-Wave wireless communication system.