Research On Adaptive Filter Based On Field Programmable Gate Array

Adaptive filters are widely used in many fields because they can track unknown signal characteristics and automatically adjust to the best filtering effect,such as signal prediction decomposition,noise cancellation,audio and video processing,etc.In view of the requirements of adaptive filter real-time and computing speed,FPGA and DSP have become the mainstream platform for adaptive filter hardware implementation,and this dissertation realizes the adaptive notch design for power frequency interference filtering based on the FPGA platform of EP4CE15F17C8.The research content of the FPGA-based adaptive filters can be divided into two aspects:one is algorithm innovation and optimization that is easy for the FPGA to implement,and the other is the engineering implementation based on the FPGA,taking into account algorithm and hardware resources.The specific work is as follows:1.Based on the relevant theory of adaptive filter,the adaptive filter algorithm(RLS algorithm,LMS algorithm)is studied in depth,and it is found that the convergence speed of RLS algorithm is better than that of LMS algorithm,but the algorithm structure is complex and the amount of operation is large,and it is difficult to implement it by the FPGA,while the LMS algorithm is easy to implement by the FPGA.The focus of this dissertation is to achieve the same performance as the RLS algorithm through optimization in view of the contradiction between convergence speed and steady-state error of LMS algorithm.At the same time,taking multiplication resource analysis as the cornerstone,the balance between numerical performance and design cost is analyzed,and the fixed-point number is determined as the data format for the FPGA design.2.Through the research and analysis of the existing variable step size(VSS)LMS algorithm,using the variance model and the momentum term of literature [30],the step size factor in the LMS algorithm is μ Two new step size parameter models are modified.The nonlinear relationship between the step size and the error signal is established by translation,inversion and flipping,which conforms to the step size adjustment criterion that the step size factor increases first and then decreases.The cubic difference LMS algorithm(cdlms algorithm)and variance LMS algorithm(srlms algorithm)are proposed.The experimental results show that the initial convergence speed of cdlms algorithm and srlms algorithm proposed in this paper is increased by 5～6 times and 2～3 times respectively compared with LMS algorithm and NLMS algorithm,and can overcome the problem of waveform peak distortion in reference [23],and the filtering effect is better.3.The feasibility and accuracy of the FPGA implementation of srlms adaptive filter are verified.The srlms adaptive filter is designed by hierarchical and modular reuse methods.The srlms algorithm is rewritten to make it more consistent with the FPGA design principles in order to reduce the design complexity.The addition tree design method is used to insert the register to reduce the delay and improve the operation speed.The experimental results show that the design method can effectively recover the target signal,and is consistent with the expected results.4.Taking the adaptive notch to filter out power frequency interference as a specific application case,a signed number array multiplier is designed based on the symbolic LMS algorithm,and the same filtering effect is achieved under the condition of limited hardware resources.The measured data shows that the hardware platform can effectively restore the target signal,and compared with the popular adaptive notch,the required multiplier resources are reduced by 7%.