Implementation Of Subband Adaptive Filters On FPGA

Adaptive filtering theory is one of the most popular research subjects in adaptive signal processing. Adaptive filtering is widely used in system identification, signal separation, channel equalization and echo cancellation and other fields. Fast convergence rate and low computational complexity as well as good numerical stability of the adaptive filtering algorithm are the goal which we constantly strive to pursue. With the advent of the field-programmable gate array (Field programmable gate array, FPGA) and EDA technologies, the development of adaptive filter will be more and more rapid.The adaptive filter principle, structure and commonly used algorithms are presented in this paper and four specific examples are also introduced as the application of adaptive filter. Then three algorithms namely the steepest descent algorithm, LMS algorithm and NLMS algorithm are described in detail. The parameters affecting the performance of the algorithm are also simulated and analyzed according to the typical application. In addition, comparisons are made among the three algorithms through simulated experiment.Open-loop and closed-loop sub-band decomposition adaptive filters are introduced in this paper. Three typical open-loop sub-band structure adaptive filters and adaptive filter based on traditional LMS algorithm are discussed on computational complexity and convergence properties. Then the sub-band adaptive filter adopted by the present paper is obtained.By using DSP Builder of Altera Corporation dedicated DSP development tools, we realized integral modeling and integral module of the two sub-band adaptive filters. To reduce the computational complexity, when the decimation filter and interpolation filter is modelled, we take efficient polyphase decimation filter and interpolation filter structure; when the weight update subsystem is modelled, the pipeline design approach is taken in order to further improve the design efficiency. In addition to, the issues of model'width is emphatically discussed. The design is proven correct through model simulation and functional simulation.The maximum clock frequency of Cyclone III devices EP3C80F484C6 chip is optimized by the QuartusⅡsoftware in terms of the logic synthesis rate, place and routing, netlist optimization and physical synthesis and logic lock technology etc. The maximum clock frequency of chip is seventeen MHz.