Package Structure Design And Thermal-mechanical Reliability Analysis Of Large-size CMOS Image Sensor Modeling

CMOS image sensor is a high-performance image processing device that can convert digital images into reliable electrical signals and has a wide range of applications in consumer electronics,the Internet of Things,and security monitoring.Traditional CMOS packages have problems such as large structure,warpage,and complex process flow,which can no longer meet the high performance and miniaturization requirements of largesize CMOS image sensors.In view of the above problems,a package structure and process scheme suitable for a large-size CMOS image sensor chip is proposed,and the thermal performance of the package structure is analyzed and studied by finite element simulation method,and finally,the manufacturability and feasibility of the package structure are verified by experiments.The main research contents of this paper are as follows:(1)Based on the packaging method of the molded sealing window,three package structures are designed for large-size CMOS image sensor chips,and the package structures are QFN and BGA packages.The QFN package size is 16×16×1.193 mm,and the BGA package structure is 15.5×15.5×1.14 mm.The package volume of BGA is10.32% smaller than that of QFN.(2)Select the large-size CMOS chip of a domestic company as the packaging object and design the process flow and package structure according to the package design criteria.The process includes three packaging solutions: The first option is to bond the UV film to the photosensitive area,the second option is to make the base with a plastic sealing machine and paste the glass on the front of the base and the lead frame on the back,and the third option is to replace the lead frame with a substrate.The content of the package structure design mainly includes a lead frame,glue pattern,wire bonding position,and overall package shape.(3)Finite element simulation analyzes the thermal performance of package structures.Firstly,the thermal performance of three different package structures is analyzed,and it can be seen from the simulation results that the package stress and warpage value of Model1 are minima,the stress and warpage values of Model 3 are the largest,the heat dissipation capacity is the best,and the heat dissipation capacity of Model 2 is the worst,and the thermal and mechanical properties of the three package structures meet the packaging requirements.Then select Model 1 for single-variable simulation analysis,and the results show that the main factor affecting package warpage is the thermal expansion coefficient of the material.The main factor affecting the thermal resistance is the thermal conductivity of the material,and the power consumption of the chip has basically no effect on the thermal resistance,which greatly influences the junction temperature of the chip.(4)According to the design of the packaging process,under the existing packaging equipment and material conditions,the verification process of part of the packaging process has been completed.It mainly includes chip bonding,wire bonding,molding,and cutting and forming.The experimental results show that each process can be completed and achieve the predetermined goal,and the packaged product is manufacturable.The three package structures designed in this paper are suitable for a single large-size CMOS chip,and the simulation analysis and some process verification analysis results provide a reference value for large-size CMOS image sensor packaging.