Research And Design Of A CMOS Frond-End Angle Sensor

Angle sensors based on vertical Hall devices are widely used in automotive and aerospace applications because of their many advantages such as full integration,low cost,and small size.In recent years,with the development of angle sensors toward high integration,high accuracy,and small size,there are still many problems in device offset,gain error,and the accuracy of digital readout circuits of vertical angle sensors.In this thesis,according to the development trend of angle sensors,the analog front-end readout circuit and analog/digital readout circuit with offset elimination and linear amplification are researched and designed,and the main research contents are as follows:(1)Research of the offset cancellation and signal modulation techniques based on four-phase rotating current and differential-differential amplification.To reduce the effects of the large offsets and low magnetic field sensitivity of the vertical Hall devices,firstly,the sine and cosine values of the angle(magnetic field strengths in X and Y directions)are detected by four vertical Hall devices,and the four-phase rotating current technique is used to separate the offset of the Hall device from useful Hall voltage,the inverse polarity offset elimination is achieved by the addition of the dual input of the DDA(differential differential amplifier).Then,the Hall voltage is amplified by the DDA using the correlated double sampling circuit and sample-and-hold subtractor to achieve the same polarity offset cancellation,while demodulating and separating the Hall voltage in the X and Y directions.And finally,the high-frequency offset and noise are filtered through the low-pass filter,so the Hall voltage has excellent linearity and minimal residual offset.Meanwhile,the chopping technology is applied in the DDA,significantly reducing the low-frequency offset and noise of DDA.Simulation results show the offset of the DDA is only 330 μV and the intra-band integral noise is only 4.6 μV.In addition,a multiplexed amplifier is designed to realize the amplification of the Hall voltage in the X and Y directions,this ensures that the sensitivity of the magnetic field in both directions is almost equal,which improves the calculation accuracy of the subsequent angular algorithm and the area efficiency of the chip.As a result,based on the 180 nm standard CMOS process,the post-simulation results show magnetic field sensitivity of 12 V/T,residual offset as low as 62 μT,and linearity of99.99% in both directions.(2)Research of high-precision analog/digital readout technology.In this thesis,a high-precision16-bit pipeline ADC is designed.In the pipelined ADC,using a structure of gain bootstrap technology in the amplifier of the Multiplier Data-to-Analog(MDAC)of the first stage achieves a loop gain of106 d B and a loop bandwidth of 529 MHz.In addition,the comparator in the sub-ADC uses preamplification and latches to enable fast settling;Moreover,to ensure the SNR of pipelined ADC,a low-jitter clock receiver circuit is designed to provide the operating clock for the pipelined ADC,and the post-simulation shows that the clock jitter of this circuit is only 75 fs.As a result,the measured Fast Fourier Transform(FFT)with a 60MS/s sine input signal at a sampling rate of 125 MS/s,the post-simulation results show that the Total Harmonic Distortion(THD)and Signal-to-Noise-andDistortion Ratio(SNDR)of the designed pipelined ADC is 119.3 d B and 88.9 d B,respectively.The Effective Number of Bits(ENOB)of ADC is 14.01 bits.At the same time,the angle calculation error is greatly reduced by using the 16-iteration Coordinate Rotation of Digital Computer(CORDIC).Finally,the angle detection resolution of 0.3° can be obtained after the post-simulation of digital-toanalog mixing.