CMOS Vertical Hall Sensors′ Design Based On Four-phase Spinning Current Technique

Hall sensors fabricated in standard CMOS process become research focus for its low cost,anti-interference ability, high integration, etc. However, compared to the bipolar and other special process, Hall device fabricated in CMOS process has low sensitivity and large offset, especially for the vertical Hall device. Therefore, the study of high-performance CMOS vertical Hall sensors has become an important task for contemporary researchers. In this paper, main works are as follow:Firstly, optimize vertical Hall device to improve the sensitivity and decrease the Hall offset. Based on 0.8 μm high voltage CMOS process, the optimized sensor achieves voltage related sensitivities of about 0.042V/(VT),current related sensitivities up to 92V/(AT) and the offset is only tens of millivolts. Secondly, a PSPICE model is established for six-contact vertical Hall device in order to facilitate circuit simulation. The model includes most of the parasitic effects, such as mechanical stress, thermal drift and junction field. Therefore it can accurately simulate the basic behavior of the Hall device and simulate error is lower than 5%. Thirdly, a novel Hall dynamic offset cancellation circuit based on four-phase spinning current technique is designed. This technology is particularly efficient for offset induced by junction field effect and its residual offset is smaller.In this paper, a fully integrated vertical Hall chip is realized. After circuit and layout design with 0.8 μm high voltage CMOS process and 5V power supply, the pre-simulation and post-simulation are conducted. The simulation results show that this circuit can effectively remove the offset voltage and linearly amplify the Hall signal. The residual offset is lower than 0.2 mT, and the linearity is up to 99.9%. Compare to two-phase spinning current, a low residual offset is achieved.