Research On The Integrated Technology Of Two-layer Chip Stacking Bonding And On-chip TSV Fillin

With the rapid development of microelectronics technology with integrated circuits as the core,the semiconductor industry has entered the "post Moore era".Three-dimensional integrated technology has gradually entered the field of vision and is recognized as one of the most important tracks for the rapid development of the semiconductor industry in the future.In recent years,three-dimensional integration technology,especially three-dimensional heterogeneous integration technology,has received widespread attention.Heterogeneous integration technology based on Chiplet has begun to develop in a standardized manner.Based on the exploration of copper electroplating technology,this paper studies an integrated technology scheme for simultaneous realization of two-layer chip stack bonding and on-chip TSV filling.The Cu-Cu interface free bonding of two-layer stacked chips is realized at room temperature,forming an integrated three-dimensional metal interconnection structure,avoiding the impact of high-temperature processes and bonding interfaces on system reliability,which has very important scientific significance and practical value.Firstly,this paper investigates low-temperature bonding technologies such as direct bonding,surface activated bonding,viscose hybrid bonding,nanostructured bonding,electroplating bonding,and TSV filling technology in 3D integration at home and abroad.Secondly,based on the process simulation software Silvaco,the feasibility of the TSV preparation process was verified by simulation,the electroplating theory was analyzed and simplified based on Faraday’s first and second laws,and the feasibility of electroplating filling was analyzed based on multi-physical field simulation and related data,providing a theoretical basis for future research and feasibility evaluation.In addition,a complete TSV preparation process plan was proposed,focusing on in-depth research on the TSV sidewall scallop pattern optimization and TSV sidewall uniform barrier layer optimization,and corresponding optimized experimental plans were proposed.Moreover,sufficient experimental research and testing analysis have been carried out on the two-layer chip stack bonding technology based on the copper electroplating process.The working mechanism of the scheme has been simulated and analyzed in combination with multi-physical field simulation.The experiment has been optimized by changing the bonding shape and reducing the aspect ratio to improve the bonding filling effect.Finally,based on the research results of various parts,a technical scheme for realizing Cu-Cu interface free bonding of stacked chips at room temperature based on copper electroplating process was proposed,and relevant experimental research was carried out.Based on the same process,the chip stack Cu-Cu bonding is realized while the TSV metal core is filled,forming an integrated three-dimensional metal interconnection.The work was conducted through a combination of experiments and simulations.The experimental samples were characterized and analyzed by using X-ray scanning,ultrasonic scanning microscopy(SAM),scanning electron microscopy(SEM),electron microscopy,shear force testing,electrical resistance testing,and infrared thermal imaging methods.The test results verified the feasibility of the research scheme.