Electroplating bonding technology for chip interconnect, wafer level packaging and interconnect layer structures

The motivation of this research is to develop a new zero-level packaging scheme that addresses three of the critical challenges facing electronic packaging today: mechanical and thermal management, environmental manufacturing issues, and compactness coupled with parasitic reduction. The approach taken will involve the utilization of MEMS-based structures and manufacturing techniques to create new types of interconnect and interconnect bonding approaches.; In this thesis, Electroplating Bonding Technology (EBT) will be introduced as a chip-to-board interconnect method and a fabrication method for micro devices in the interconnect layer or inter-substrate layer. To illustrate the technology, an array of metal interconnects fabricated with surface micromachining and electroplating on two substrates has been transferred to bonded and united metal structures with inter-substrate-Cu electroplating.; In conventional chip scale packaging, improvement in the bonding material, mechanical, and electrical properties, as well as reduction in processing cost of chip interconnect is required. EBT offers several advantages which act to improve these critical issues, and these advantages are demonstrated in this thesis by means of fabricated test structures. The electroplating bonded chip interconnect system has been developed with both mechanical and electrical test structures and integrated thermal reliability measurement structures. Of particular note is the ability to use MEMS technology approaches to fabricate flexible interconnects between chip and board, so as to accommodate the large thermal expansion effects expected for the next generation of large-area, high-temperature-operation integrated circuits.; Furthermore, the technology has been utilized to fabricate micro devices in the interlayer of two separated substrates for maintaining system functionality while simultaneously taking up no real estate on either substrate. To illustrate this concept, electroplating bonded MEMS solenoid inductors have been built, which not only are located entirely within the interconnect layer, but also exploit the relatively large chip-to-board gap to achieve inductance values and quality-factor values exceeding those achievable using other approaches.