Research On Through Silicon Via Fabrication And Low Temperature Copper Nanostructure Bonding For 3D Integration

The productivity and performance of microelectronics products have been continuously developed in the past few decades following Moore's Law.However,with the increase of electronic device size and chip integration,the chip feature size approaches the physical limit.The traditional packaging technology can not solve the interconnection delay and power consumption caused by the performance and cost issues.Three-dimensional integration technology is expected to become the most promising system-level integration program due to its advantages of high performance,low power consumption,and low manufacturing cost.In this study,we focused on the through silicon via(TSV)and low-temperature bonding technologies for three-dimensional integration.Morphology control of TSV with small diameter was studied,defect-free TSV copper filling scheme with high efficiency was realized,and feasible low-temperature bonding methods by introducing Cu nanostructures were successfully developed.The specific researches include:(1)The etching process optimization and efficient copper filling of small diameter TSV arrays were studied.TSVs were etched by deep reactive ion etching,and the influence of different process parameters on the roughness of the TSV sidewall was studied.The formation and growth law of large-scale rough structures on the sidewall were investigated,the sidewall was successfully improved by the optimization of the process parameters,and small diameter and high aspect ratio TSV arrays were successfully obtained.Then TSV arrays were filled with copper by electroplating.The influence of different process conditions including pre-wetting methods,coverage of seed layer,fluidity of plating solution and current density on the quality of copper-filled TSVs were studied.An improved two-step electroplating process was demonstrated to effectively reduce the electroplating time and the thickness of the overburden on the wafer surface.With these optimized processes,we realized defect-free TSV copper filling with high efficiency.(2)Novel Cu/Cu and Cu/Sn low temperature bonding methods by introducing Cu nanostructures(Cu nanorods and Cu nanowires)were successfully developed.Cu nanorods were fabricated by an oblique deposition method,and the mechanism of low temperature Cu nanorod bonding was explained by analyzing the intermetallic compound growth difference after the introduction of nanorods.Then we proposed to use Cu nanorods for realizing low temperature Cu/Cu and Cu/Sn bonding.The results showed that Cu/Cu bonding was successfully achieved at the bonding temperatures of 250?350 ? with the maximum bonding strength more than 20 MPa,and Cu/Sn bonding was successfully achieved at the bonding temperatures of 150?300 ? with the maximum bonding strength more than 44.4 MPa.Moreover,the bonding environment in Cu/Sn bonding was successfully extended from protective atmosphere to air environment after the introduction of Cu nanorods.Cu nanowires were fabricated by a novel low temperature,template-less method through a hydrogen thermal decomposition-reduction route of Cu(OH)2?CuO?Cu.The low temperature melting behavior of Cu nanowires under different atmospheres was studied,and the mechanism of low temperature Cu/Cu bonding by the Cu nanowires was explained.After that,Cu nanowires were introduced to decrease the interconnection melting point and the requirement of coplanarity,and we successfully achieved reliable Cu/Cu bonding 150?400 ? with the maximum bonding strength more than 44.4 MPa.(3)Combined with the above processes,the inter-chip stacking of TSVs and microbumps was realized.The Cu nanorod/Sn bonding was successfully extended to microbumps,and Cu nanorod/Sn microbump bonding was realized at the bonding temperature of 250 ? in which the bonding interface was tightly connected.After that,a new process scheme of TSV copper filling and micro-bump fabrication was proposed.A one-step electroplating method was adopted to realize defect-free TSV copper filling and microbump fabrication simultaneously,which simplified the traditional process and reduced the preparation cost.Based on the above methods,a two-layer stacking of TSVs and microbumps was realized.These research results are of great significance to the development of high density three-dimensional interconnection technology.