| The visual object tracking system is an innovative and widely used intelligent system in the field of image algorithms and engineering.With continuous progress and mutual empowerment in technologies such as visual algorithms,modeling platforms,sensors,processor architectures,and integrated circuits,visual object tracking systems have been widely applied in fields such as security monitoring,autonomous navigation,industrial inspection and classification,military reconnaissance,military precision guidance,and aerospace engineering.The visual object tracking algorithm often involves important processes such as format conversion,pre-processing,feature extraction and recognition,and intelligent tracking,among which pre-processing is an important guarantee for high-precision feature extraction and accurate tracking.Under the requirement of high precision,there are higher requirements for image denoising quality.Constrained by performance and cost on the PC side,heterogeneous implementation of image algorithms has become a research hotspot,mainly focusing on high-speed and lowcost research directions,including implementation solutions represented by ASIC,FPGA,and ARM platforms.With the increase in algorithm complexity,the power consumption of heterogeneous implementation will become a constraint on performance and endurance improvement.Excessive power consumption will inevitably cause endurance difficulties and cumulative losses in circuit system noise,and cooling costs will increase accordingly.Therefore,low-power optimization of the system is of great significance.Accurate and efficient object tracking system is an important guarantee for completing basic tasks.In this thesis,a system program strategy was formulated based on the requirements,and an image transmission system based on FPGA was studied and implemented to provide a basic platform for heterogeneous acceleration and power optimization of core algorithm circuits.In response to existing problems such as poor video denoising and fidelity effects,low efficiency of visual algorithm implementation on traditional hardware platforms,and high system power consumption leading to reliability crises,the main innovations and work completed are as follows:(1)A dual-filtering algorithm model with signal-to-noise ratio and engineering performance advantages is proposed for feature detection and recognition in visual object tracking systems,which require high image quality.Firstly,the model characteristics and representation of filtering algorithms are studied and analyzed,and important factors affecting feature detection efficiency are extracted collaboratively.In order to accurately evaluate the essential characteristics of the model,a robust modeling evaluation test platform for this system is designed.Secondly,the filtering algorithm is optimized based on noise characteristics,and a dual-filtering algorithm model is established,aimed at minimizing nonlinear noise while maintaining image representation characteristics,by optimizing pixel weighting and fusion algorithm advantages.Finally,the algorithm model is evaluated and compared for reliability using the modeling evaluation platform,and the actual characterization effect is verified at the edge computing end.Experimental results show that the filtering algorithm model proposed in this thesis exhibits certain signal-to-noise ratio advantages on the algorithm evaluation platform,averaging 2.6 times better than traditional median,mean,and Gaussian filtering algorithms on feature maps,which helps improve feature detection and tracking efficiency.(2)In order to improve the performance and accuracy of visual target detection and tracking system,and reduce the overall cost and power consumption,a target tracking algorithm based on FPGA heterogeneous platform acceleration strategy is proposed.Firstly,the behavior level of the target tracking system algorithm modeling model is analyzed.Reasonable module division is carried out by combining algorithm and hardware characteristics.According to the requirements,the system-level and module-level SPEC documents are formulated,and the design specifications such as circuit architecture,interface,timing,resource usage and performance indicators are formulated.Secondly,based on hierarchical design and bottom-up design strategy,RTL high-quality digital circuit design is carried out from module level to system level.The verification platform is built for each stage module.Then,a comprehensive constraint script is designed for specific process library parameters for comprehensive mapping and static timing analysis.It aims to ensure the timing convergence of the circuit and improve the performance and anti-interference characteristics of the target tracking system.Finally,based on the gate-level netlist,the bit stream file is generated for FPGA prototype verification.The experimental results show that under the guidance of rigorous digital circuit design process strategy,the performance of target tracking heterogeneous system is better.The real-time performance of the system is 28.4 times that of i7-7700 CPU,and the resource overhead is controllable.The target convergence rate increased by 81.3 %,and the real-time processing frame rate can reach 60 fps / s.Therefore,the heterogeneous system has certain innovation and application value.(3)In order to address the sensitivity of edge computing system performance,battery life and cost to power consumption,a low-power design strategy based on heterogeneous acceleration system is proposed.Firstly,the classification and physical mechanism of digital circuit power consumption are studied.Secondly,based on the optimization program and strategy of digital circuit power consumption principle and system characteristics,a combined low-power design strategy for system-level,behavioral-level and RTL-level based on heterogeneous system is proposed.Finally,graded low-power design is conducted according to the program,and the design results are verified and analyzed.The experimental results show that the system power consumption optimized based on the combined low-power design strategy performs well,and the internal power consumption of the system is reduced by 15%.This system has obvious power consumption advantages among many vision systems implemented based on hardware platforms and can effectively improve system stability and battery life. |
