Mechanism And Characterization Of Integrated SBD Dual Siot SiC MOSFET

Silicon carbide(SiC)has wide band gap,high thermal conductivity,high critical breakdown field strength,high saturated electron drift speed and other characteristics,with its excellent physical characteristics can be produced high pressure,high temperature,high frequency of high power devices.At present,SiC MOSFET devices have a wide range of application prospects and values in the fields of new energy power generation,photovoltaic power generation and rail transit.The double-channel SiC MOSFET has the advantages of low on-pass resistance and good reliability of gate oxygen,but the gate leakage capac ity of the device is large,and the bipolar degradation occurs in the reverse on-pass.Aiming at the above problems,an integrated SBD double-groove SiC MOSFET structure is proposed,and studies its working mechanism,current transport mechanism and device characteristics.The main research contents and achievements are as follows:Firstly,Summarize the research progress at home and abroad,and summarize the existing problems and solutions of SiC MOSFET.The working mechanism and current transport mechanism of double slotted SiC MOSFET(Double slotted SiC MOSFET,DT-MOSFET)devices are analyzed.The static and dynamic characteristics of DT-MOS are studied,including positive and blocking characteristics,Blocking characteristic,gate leakage capacity,gate charge and switching characteristics.Finally,the avalanche failure mechanism of devices is analyzed.Secondly,An integrated SBD double slotted SiC MOSFET(Integrated SBD dual slot SiC MOSFET,SPDT-MOS)structure is proposed.On the basis of using shield gate to improve the switching characteristics of devices,SPDT-MOS optimizes the L-shaped source slot into a type PSR layer,and adds a current extension layer to expand the conduction path of the source wall current,and improves the disadvantage of reducing the conduction path at the bottom of the grid due to the shield gate.In the blocking state,the PN junction formed by PSR layer and drift layer can withstand voltage,improve the reliability of grid oxygen,and realize the compromise optimization of on-going resistance and breakdown voltage.In addition,SPDT-MOS integrates SBD on the side wall of the source pole,which effectively reduces the cell size and avoids bipolar degradation of the device,thus realizing the overall performance optimization of the device.The results show that,compared with PDT-MOS,SPDT-MOS can reduce the on-resistance by 42.8%while maintaining the high voltage of the device,and achieve the compromise optimization of on-resistance and breakdown voltage.Compared with DT-MOS gate leakage capacity decreased by 81.2%,gate charge decreased by 41.2%,and backchannel opening voltage decreased by 42.3%,and excellent dynamic characteristics were obtained.Thirdly,According to the structural characteristics of SPDT-MOS devices,the key parameters that affect the performance of devices are analyzed,including the depth of gate,the depth of shield gate,the width of shield gate,the doping concentration of Ncsl layer,the width of PSR layer,etc.The simulation results show that when DGatel is 1.25μm,DGate2 is 1.5μm,WGate2 is 0.8μm,Ncsl is 1×16cm-3,LPSR is 1.4μm,the static and dynamic characteristics of the device are optimal.Finally,dynamic avalanche failure analysis of SPDT-MOS is performed,and the results show that the critical pulse width of the device is 15μs.