Design Of A 12bit Segmented Resistive Divider DAC

Today,with the increasing development of information technology,digital signals have become the optimal solution for data transmission due to their high interference immunity and other advantages,but since analog signals are commonly found in nature,data converters have come into being.With the increasing demand for analog and digital signal processing,information processing systems are putting higher demands on data converters in terms of high accuracy,high speed,and low power consumption.In this paper,we design a 12-bit segmented resistive divider digital-to-analog converter(DAC)with a segmentation ratio of "7MSB+5LSB",which can operate at a clock rate of up to 30MSPS;it is powered by a single 5V power supply to achieve a rail-to-rail output range and consumes only 0.55 m A of current under normal operation;it has a built-in low-temperature drift bandgap reference voltage source for off-chip use with a reference output of 2.5V;and it is fabricated in a 0.6μm CMOS process with a 1375×1815μm2 layout area.In this paper,after giving the performance index requirements of the design,the main components of the DAC circuit are determined,including analog circuit modules such as bandgap reference module,trim module,DAC conversion core module,output op-amp module,and digital modules such as shift registers.The design scheme,circuit structure and pre-simulation results of each major module are elaborated.For the bandgap reference module,based on the traditional bandgap reference structure,this paper uses the VBE difference to generate a current containing nonlinear components superimposed on the reference voltage output for second-order curvature compensation,and completes a low-temperature drift bandgap reference voltage source for off-chip use.In addition,a digital tuning circuit is designed for the process drift phenomenon,and the temperature coefficient and voltage value of the reference voltage can be tuned by entering a serial code after the chip is packaged.For the DAC conversion core module,firstly,based on the analysis of the sources of nonlinear error and the factors affecting the nonlinear error of the segmented resistor divider structure,the area of the unit resistor is planned reasonably with the resistor process deviation provided by the process manufacturer to ensure the design requirement of low nonlinear error.Secondly,to address the problem that the internal resistance of the NMOS switch in the DAC core shows a nonlinear increasing trend from the lowest to the highest bit with the change of the gate source voltage and source lining voltage,which introduces unnecessary nonlinear errors,the switch size is re-planned to minimize its impact.The DAC layout is then designed and verified by post-simulation with the extracted layout netlist.The post-simulation results are less different from the pre-simulation results and can meet the design specifications.Finally,we adopted the SOP8 structure in the form of plastic package and completed the finished product testing of 20 chip prototypes.The test results show that all the prototypes can realize 12-bit data conversion and function correctly.The error of Differential Non-Linearity(DNL)is within±0.25 LSB and the error of Integral Non-Linearity(INL)is within ±2LSB at room temperature.Under the condition of 5V supply voltage,the normal operation consumes at most 0.56 m A of static current,and the temperature coefficient of the trimmed reference voltage can be as low as 2.1ppm/℃ in the temperature range of-55℃~+125℃,and the deviation of the reference voltage is less than 0.2% to meet the design requirements.