| In recent years,with the rapid development of wireless communication technology,the number of mobile terminals has grown exponentially.In wireless communication systems,the power amplifier(PA)serves as the last stage of the transmitter,exhibiting the strongest nonlinearity and the highest working power,which directly determines the performance of the entire wireless transmitter.The continuously evolving communication technology has imposed higher performance requirements on power amplifiers.As a result,power amplifiers have consistently been a research hotspot in the field of wireless communication technology.The SOI-LDMOS process is a technique that integrates LDMOS power devices under a 0.13 μm SOI process.In the early 21 st century,LDMOS,characterized by high breakdown voltage and high reliability,became the preferred choice for base station power amplifiers.However,this technology faced issues of large parasitic effects and strong nonlinearity.Consequently,most of the current mainstream mobile terminal power amplifiers are made of III-V compound semiconductors.Nevertheless,the emergence of the SOI-LDMOS process combines the advantages of higher isolation degree offered by the SOI process and the high breakdown voltage of LDMOS,which enables integrating power amplifiers with RF switch modules,achieving higher integration and lower cost.This thesis primarily focuses on the commercial power amplifier applications in the sub-6G frequency range from 2.3 GHz to 2.7 GHz,with particular emphasis on linearity,bandwidth,and efficiency problems of the power amplifiers in this frequency range.To address the issues of strong nonlinearity and large parasitic effects in LDMOS,this thesis investigates the linearization method for LDMOS power amplifiers based on adaptive bias technology and studies the wideband application and efficiency improvement methods for LDMOS based on impedance compensation technology.Firstly,the thesis conducts research on the linearization technology of LDMOS power amplifiers and completes a single-ended integrated LDMOS power amplifier design.In response to the rapid power compression and inconsistent slope of LDMOS,this thesis innovatively proposes a segmented adaptive bias circuit and designs a high-speed operational amplifier as a buffer.This ensures that the adaptive bias output can be transmitted to the gate with minimal delay and promptly absorb the low-frequency nonlinear components of the gate node.The power amplifier achieves a 1d B compression point of 29.5d Bm within the working bandwidth and phase distortion within 4。.Subsequently,the thesis studies the bandwidth and efficiency problems of LDMOS power amplifiers and completes an integrated LDMOS power amplifier design based on a differential structure.The design employs transformer matching to achieve broadband response and innovatively applies Class-E impedance compensation technology to interstage matching,realizing a 3d B small-signal bandwidth from 1.14 GHz to 3.5 GHz.By adjusting the input impedance of the output stage using techniques such as neutralization capacitance,the design achieves a saturated output power of 33.28 d Bm and a peak added efficiency of 51.76% within our target frequency range of 2.3 GHz to 2.7 GHz. |
