| With the continuous development of semiconductor-integrated technology,the complexity of modern communication systems is increasing.The shared bus structure of traditional System-on-Chip(So C)is difficult to meet the increasingly complex communication needs.As a reliable communication network paradigm,Network-on-Chip(No C)is proposed to solve the bus architecture problem of So C,which can be applied to the field of communication signal processing to meet more stringent performance requirements.The topology,routing mechanism,and mapping algorithm are the key to the research field of No C.Once the topology and routing mechanism of No C are determined,the performance of No C is largely determined by the mapping algorithm,so the mapping algorithm is very important in No C design.This thesis studies the No C task mapping algorithm in the field of communication signal processing.The main research contents are as follows:(1)Aiming at the problem that the search space of No C task mapping is too large,and the commonly used genetic algorithm(GA)is not easy to jump out of the local optimal solution and lead to premature convergence,this thesis proposes a mapping optimization algorithm based on improved genetic algorithm(IGA),so as to optimize the delay and power performance indicators.Different from GA,IGA uses the proposed initial population generation technology to obtain higher quality initial population,and uses the niche technology based on Affinity Propagation(AP)algorithm to improve the selection and crossover operation of GA,so as to improve the search efficiency of GA and promote its iterative convergence process.Here,three typical mapping examples related to communication signal processing are selected for simulation experiments.The experimental results show that under the same multi-objective optimization mapping model for the delay and power consumption,IGA has achieved significant performance improvement compared with the optimal solution obtained by GA and simulated annealing algorithm.The average delay is reduced by 26.76% and 20.09% respectively,while the power consumption is reduced by 42.99% and 34.92% respectively;(2)Aiming at the incremental scenarios in practical applications,that is,adding new functions to the deployed multi-core platforms,because the commonly used mapping algorithms cannot meet the actual incremental requirements well,this thesis proposes an elastic time slot incremental mapping algorithm based on the time slot interpolation space mapping algorithm.The incremental mapping scheme for different incremental scenarios is obtained by static mapping,and the task is deployed offline to realize the rapid operation of incremental functions in actual operation.The proposed algorithm makes full use of the idle time slots on each processing unit and the parallel computing advantages of the multi-core platform,so as to obtain the task mapping scheme of new functions without affecting the deployed functions.While improving the resource utilization of the multi-core platform,it makes greater use of the parallel computing advantages of the platform to provide services for task operation.The simulation results show that the elastic time slot incremental mapping has a very good performance advantage compared with the fixed time slot incremental mapping and the general incremental mapping.The delay is reduced by 5.89% and 77.43% respectively,the power consumption is reduced by 12.35% and 9.22% respectively,and the resource utilization is increased by 2.98% and 11.98% respectively. |
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