Research On Image Denoising Processing Of Near-Infrared Photoelectric Detection Array Based On FPGA

Near-infrared digital image processing is a method of processing near-infrared images using computer software or emerging hardware microprocessors.It includes areas such as image restoration,image reconstruction,image analysis,pattern recognition,and computer vision.Among them,image denoising,as a branch of image restoration,is widely used in fields such as medicine,military,and industry.Filtering algorithms are the core of image denoising,but traditional digital image denoising systems are mainly based on software platforms and cannot meet the high real-time requirements in some applications.Therefore,implementing fast digital image denoising on hardware-based platforms,while meeting real-time requirements and reducing hardware resource consumption,has become an important topic in image processing research.This thesis proposes a FPGA-based method for noise reduction of images generated by a near-infrared photoelectric detection array.Compared with PC software platforms,FPGA can achieve higher processing speed at lower operating frequencies and perform parallel processing and output of digital image pixels.Based on in-depth research on traditional digital image noise reduction algorithms,this thesis selects median filter algorithm as the noise reduction algorithm(especially for salt-and-pepper noise)for digital images,and improves it to make it more suitable for implementation on FPGA hardware platform.The key to the design of this system is the improved fast median filter algorithm,which can obtain the median result of the 3x3 fast median filter template window in three rounds of 21 comparisons,simplifying the calculation process,saving hardware resources,and improving the system’s timing performance.The entire noise reduction system consists of three main modules: CMOS video image buffer module,fast median filter algorithm module,and DDR3 DRAM control module.The fast median filter algorithm module is the main design module of the algorithm.Some modules introduce FPGA pipeline design thinking and ping-pong transmission principle to improve the system’s data transmission throughput and ensure good timing performance.This thesis uses ISE Design Suite 14.7 as the development environment and Xilinx’s Spartan-6 series FPGA chip XC6SLX16-2CSG324 as the FPGA core.This chip has low power consumption,low cost,and rich hardware resource configuration.Verilog HDL is used to describe and implement each module,including describing the fast median filtering algorithm with hardware structures,connecting interface signals and matching timing,and designing internal logic of each module.The system fully utilizes the on-chip and off-chip memory devices of the FPGA,saving hardware resources and simplifying logic design while meeting the design requirements.During the implementation process,functional simulation verification is performed on the Model Sim platform,and then on-board verification is performed through synthesis and layout.Finally,a fast median filtering system based on FPGA is implemented,with a working frequency of 110 MHz and an input of a 640×480 resolution original image.To further verify the effectiveness of the algorithm,the pre-and post-processing effects of images captured by a non-cooled infrared detector were compared to evaluate the reliability of the fast median filtering algorithm.