Digital Image Denoising And Coding Algorithm Research Based On FPGA

With digital image processing technology being applied in more and more areas,the demanding of digital image processing algorithm is increasing. Currently, mostdigital image processing algorithms can only be implemented in soft environment.However, the practical digital image processing system is required to deal with thehuge amount of data and high speed of processing, The implementation of systemwith software environment has the disadvantage of large-scale and high-cost. AndFPGA(Field Programmable Gate Array)device has low power consumption, parallelcomputing capability and high perfomimce characteristics, which is suitable fordigital image processing system implementation. Therefore, the application prospectdigital image processing algorithm based on FPGA is very broad.This paper takes digital image denoising and video coding standard to do researchand design of digital image processing algorithm implementation on FPGA.Digital image denoising: Similar block group denoising based on three-dimensionDCT(Discrete Cosine Transform). Among them, the3D-DCT is the core of thesystem，and also affects the quality of the design directly. The key point of this paper:3D-DCT is decomposed into ID-DCT of three orientations; ID-DCT achieves theutilization of integer transform matrix. This method can eliminate the floating-pointarithmetic, only use shifter and adder, and be better suitable for FPGA structure.Digital image video coding: to implement the inverse quantization and inversetransformation module of HEVC(High Efficiency Video Coding). FPGA hardwaresystem uses module and pipeline design. The key point of this paper: A unifiedarchitecture for different size blocks of image data. This method can achieve reuse ofmodule, and save hardware resources.Finally, this paper simulates the above two digital image processing hardwaresystem. And it shows the correctness and feasibility of hardware algorithms.