Research On Radar And Echo In The Loop Simulation Technology

With the complexity of application scenarios and the development of electronic technology,the functions of radar systems have become more complete,and the corresponding research and development cycle has also become longer.Moreover,the testing of radar systems has become more rigorous,which has driven the development of radar echo simulation technology.The radar echo simulator can simulate echo signals in real environments,which can quickly and conveniently test radar systems,reduce costs,and shorten the research and development process.At the same time,modern radar also puts forward higher requirements for real-time and universal signal processing.With the increasingly powerful performance of FPGA,its high parallelism and low latency gradually make it the main platform for radar signal processing.Therefore,if the echo simulation system and signal processing system are combined into a closed-loop system,on the one hand,mutual verification testing can be conducted on the two systems,and on the other hand,the two systems can also be independently experimented.The functionality of the entire closed-loop system is highly integrated,and in the case of mutual testing,the development cycle of the echo simulation system and signal processing system is greatly reduced.Based on the research topic,this thesis uses FPGA as the implementation platform to design the radar target echo simulation system and a radar signal processing system,and form an closed-loop system.The main research work is as follows:1.Designed and implemented a simulation system for target echoes,mainly introducing modules such as digital orthogonal frequency conversion,noise simulation,and target echo simulation.In terms of distance simulation of the target,DDR is packaged into a super large capacity FIFO as the main cache space,and combined with a delay matrix built using FPGA internal storage resources,long-distance target simulation is achieved.This method solves the problem of insufficient internal storage resources in FPGA in traditional distance simulation,greatly increasing the distance of target simulation2.Designed and implemented a signal processing system for pulse radar.This thesis improves the problem of weak reconstruction in conventional FPGA based processing systems,allowing the system to meet the processing needs of different formats of signals through parameter configuration.In response to the low utilization of DDR bandwidth in conventional data rearrangement,burst and row splitting data rearrangements are proposed,greatly improving the efficiency of rearrangement.3.Under the condition of fully utilizing the large bandwidth of DDR,for the scenario of multiphase input in CFAR processing,a multiphase input CFAR implementation structure and an improved low resource consumption multiphase parallel CFAR structure are proposed,which improves the performance of CFAR processing in FPGA and saves a lot of resources.3.Finally,a radar and echo closed-loop simulation system is built on the hardware platform,and experiments and tests were conducted on various functions of the system.The experimental results indicate that the designed closed-loop system can meet the required functional and performance indicators,achieving the research objectives.