Hardware Design Of VVC Reference Pixel Processing And Loop Filter Module

With the rapid development of digital video technology and the growing demand for ultra high definition video,video coding technology is becoming increasingly critical.With this background,the JVET developed a new generation of video coding standard named VVC,which has significantly improved the coding performance compared with HEVC,and its applications cover more video industries.VVC video decoding chip is a key part of the VVC industry chain and plays an important role in promoting the implementation of VVC.Therefore,as the core of VVC video decoding chip,the development of VVC video decoding IP has great application value.Based on this background,this thesis conducted in-depth studies on the hardware design and implementation of several key components in VVC video decoding IP,reference pixel processing module and loop filter module.The main work of this thesis is as follows:1.The reference pixel processing module was designed and implemented.According to the relevant algorithms,the reference pixel processing module was divided into three sub-modules: reference pixel filling,filtering and mapping modules.By designing parallel processing elements,the speed of each sub-module could be improved to provide reference pixels for the subsequent in-frame prediction module more efficiently.2.The loop filter module was designed and implemented.Based on the HEVC decoder IP,the DF and SAO modules were reused,and the hardware design of LMCS and ALF modules were added.The work for the design of LMCS module included:dividing LMCS into modules according to its algorithm;improving the way of data processing to reduce resource consumption;designing parallel operation units to increase the speed;completing multiple division operations required by the algorithm by reusing dividers to minimize area.The work for the design of ALF included: based on the ALF algorithm,proposing a 3-stage pipeline architecture with a pipeline granularity of 8×8luminance pixel blocks,and splitting the complete computation process of ALF into three sub-modules,each of which constituted one stage of the pipeline to improve the throughput rate of the design.In addition,in the design of the filtering calculation submodule,two types of filtering operations with similar templates were completed by multiplexing the operation units to reduce area consumption,and the simultaneous processing of multiple pixels was completed by parallel basic operation units to increase the processing speed.3.Based on the reference software,the verification platform was built and simulation on the design of this thesis and the VVC video decoding IP was excuted to verify the functional correctness of the design of this thesis,while the simulation results showed that the decoding speed of the video decoding IP could reach the standard of 4K 120 fps and 8K 30 fps.In addition,DC synthesis of the design in this thesis was performed under the clock frequency constraint of 800 MHz and TSMC-12 nm process library constraint to derive its area report.In this thesis,several key components of the VVC video decoding IP were investigated,which are of great significance for accelerating the development of VVC video decoding chip and promoting the application of VVC standard in the field of ultrahigh definition video.