FPGA-based Hybrid Encryption And Decryption Algorithm Implementation

In order to protect data information from malicious theft during transmission,encryption and decryption algorithms are usually used to secure data.The common encryption and decryption algorithms can be divided into symmetric and asymmetric encryption and decryption algorithms,among which,the symmetric encryption and decryption algorithms represented by DES and AES are widely used because of their fast encryption and decryption speed and simple implementation methods,but the use of a single key also makes the key transmission process has certain risks.In contrast,asymmetric encryption and decryption algorithms such as RSA algorithm can make the data more secure due to its special encryption and decryption mode of public key encryption and private key decryption,but the difficulty of implementing the algorithm and the low efficiency of encryption and decryption come with it.In order to solve the above problems of encryption and decryption algorithms,this paper designs and implements the AES-RSA hybrid encryption and decryption algorithm,and designs the related verification system to simulate and verify the function of the hybrid encryption and decryption module with ZYNQ-7000 series FPGA chips.Firstly,three different types of encryption and decryption algorithms,DES,AES and RSA,are selected and their encryption and decryption functions are implemented in C language respectively,and then the encryption and decryption modules of AES and RSA are reproduced in Verilog language,and the two designed encryption and decryption modules are imported into Vivado simulation software for simulation and testing of module functions.Based on the already designed and implemented AES and RSA encryption and decryption modules,write the AESRSA top-level module and design the AES-RSA hybrid encryption and decryption module by combining the two modules by defining the transmission of control signals and data signals.Complete the construction of FPGA test system.In this system,the ARM program stores the data in BRAM and allocates the ARM side memory mapping address for it.The hybrid encryption and decryption module extracts the data from BRAM and performs the operation,and after the encryption and decryption process,BRAM then stores the received data in the corresponding address,and finally displays the data on the host computer through the serial port.In this experiment,the FPGA test system is used to perform 5000 times of mixed encryption and decryption test with a total time of 44.7ms,and the correct rate is 100% by comparison.The proportion of logic resources consumed by the hybrid encryption and decryption module to the total resources of FPGA chip is 47.29% for LUT and 19.38% for FF.