Low-Power Design Of ASIC For RS Encoding Chip

Reed Solomon(RS)code is a widely used linear block code.Its error correction performance is excellent,and both random and burst errors can be corrected.The error correction performance of RS code in the field of medium and short code lengths can even approach theoretical values.Although there are many other mature error correction codes,RS codes still stand out in the field of satellite communications due to their excellent error correction performance.With the continuous progress of integrated circuit process nodes,the issue of power consumption is becoming increasingly prominent.The high heat caused by high power consumption can directly affect chip operation,leading to problems such as performance degradation.Therefore,how to design low complexity and low power RS encoded ASIC chips has better research significance,providing a new direction for the chip process.This article mainly focuses on the Low-Power design of a RS encoding ASIC chip based on TSMC28 nm.Firstly,the principle of RS encoding and the power consumption composition of integrated circuits are introduced,and the commonly used Low-Power methods are analyzed to obtain a Low-Power method suitable for RS encoding chips.Starting from the design level,this paper conducts Low-Power design for RS encoding chips from three aspects: System architecture,RTL level,and Gate level,and practices it in ASIC design.Combining front RTL level design with back-end physical design,this paper studies Low-Power chips that can achieve RS encoding functions.At the System architecture level,when implementing multipliers in the RS coding circuit in hardware,due to the large amount of data operations and high consumption of power consumption caused by elements in the Galois Fields,this paper proposes a method based on the multiplier factor matrix to optimize the RS coding algorithm,and performs functional verification of the optimized algorithm on FPGA;At the RTL level,the Design Compiler tool is used to logic synthesize the RTL code written,and Low-Power methods such as Clock-Gating are added;At the Gate level,Innovus tools are used,and multiple Low-Power methods such as Multi-Supply Voltage and CCopt are introduced for back-end physical design.After Static Timing Analysis,Formal Verification,and Physical Verification,the RS encoding Low-Power chip in this design uses Voltus to perform power consumption analysis on the design.There are no violations such as IR drop and Electron Migration.The overall power consumption of the chip is reduced by about 45% compared to the previous one,which can be concluded that the Low-Power design can be successfully implemented,meet the expected power consumption requirements of the chip,and ensure that it can meet the signing standards.