| In recent years,with the rapid development of applications such as the Internet of Things,Big data analysis,and Artificial Intelligence,the amount of data has exponentially increased,which puts forward higher performance requirements for the memory and processer of digital computing platforms.In the past few decades,computers have been using the traditional Von Neumann architecture.In the data-intensive applications such as artificial intelligence,separate processing and memory systems make bus data transmission the main bottleneck for system performance improvement.The in-memory computing technology effectively improves the system performance by innovating the data processing architecture,reducing the data transmission distance and frequent memory access,and has become an effective way to solve the traditional von Neumann performance bottleneck.Early in-memory computing based on traditional CMOS memory technology could not be implemented well due to some problems in volatility,integration,and cost-effectiveness.Therefore,the emergence of a new type of non-volatile memory provides a new solution for the realization of in-memory computing.Based on STT-MRAM,this paper proposes a general-purpose in-memory computing scheme based on 2T-1MTJ cell structure.By multiplexing access transistors,the control of bit logic operations is placed in the memory array,at the same time,it keeps the traditional memory function of MRAM.The main research work of this paper is as follows:1.Researched and analyzed the physical characteristics of MTJ devices and related modeling work.The MTJ device model used in circuit simulation was established using Verilog-A description language.The model mainly considered the static and dynamic characteristics of MTJ,and introduced parameter deviations for follow-up reliability analysis of the circuit.2.Comparative analysis of several typical memory cell structures,and based on the 2T-1MTJ unit,a new type of in-memory computing scheme for general-purpose（basic logic operation,like AND/OR operation）is proposed,and the same operation reference unit is used inside the memory.The scheme also includes the design of specific operation reference unit and read and write drive circuit.In addition,in order to improve the accuracy of the calculation,an optimized and improved 2T-1MTJ cell structure using dual-threshold transistors is proposed.3.To evaluate the proposed scheme’s fuction and performance,a CMOS/MTJ hybrid simulation which combines SMIC 55nm process with MTJ compact model is compared with similar schemes based on 1T1MTJ and 2T2MTJ cell structures in different MTJ process deviations,TMR,temperature and VDD.Including the correct rate of logic operations under fluctuating conditions,and the error rate of unit write operations.The research results show that the proposed in-memory calculation scheme based on the 2T-1MTJ unit structure is better than the 1T-1MTJ scheme in the above reliability analysis.And compared to the 2T-2MTJ solution,it has a higher storage density and write operation reliability.At the same time,the read and write performance of the proposed improved 2T-1MTJ unit structure solution has also been further optimized and improved.The realized scheme is expected to be applied to actual digital processing applications through further expansion. |
