Analog-Computing Architectures With On-Chip Non-Volatile Memories

Computing systems are composed of memory and computing units,and their competition in turn drives the development and evolution of the computing systems.With the advancement of digitization in recent years,the memory inherits the low mobility from its physical twin.Inmemory computing is the response to this trend.By designing a memory-centric system,data can be utilized more efficiently.The impact is that the divisions of system architecture that formed naturally in the past decades are challenged.This dissertation focuses on the coupling and decoupling in this computing architecture with a solid background of device physics.Ideas are validated on the industrial STT-MRAM(spin transfer torque-magnetic random access memory)platform and NOR flash platform.The decoupling of the physical layers,as well as the research on the decoupling of analog circuits and memory,has promoted the mass production process of in-memory-computing.The detailed work of this dissertation is as follows:1.Reliability and dynamics of the STT-MRAM writing process.STT-MRAM is one of the technology platforms used,and this work conducts in-depth research on its writing process.Inspired by the unique dynamics of STT-MRAM,we study the energy optimization problem of the writing process.Focusing on the universal problem of write reliability in memory,we carry out research on the degradation of write bit error rate and the real-time monitoring of the write process.Analysis for CIM application is given.2.Decoupling of memory and computing operations.Due to its high technology maturity,NOR flash is another important technology platform used in this paper.The writing and reading(for computing)operations of flash correspond to high voltage and low voltage respectively.With this observation,we adopt the sidewall tunneling for writing to put the destructive highvoltage operating region away from the silicon surface that is used for the low-voltage reading.This enables information storage to be less affected by defect trapping and detrapping,so that the data retention accuracy of the device can match the initial programming accuracy.We verified the effectiveness of this technique on a neural network for speech.3.Decoupling of algorithm and physical layer.In this work,we elucidate that the IR drop effect is a major source of accuracy loss and can be effectively corrected during the linear simplification.We propose two algorithms to speed up the calculation of effective conductance.Both aim to compute as few intermediate variables as possible.Based on these algorithms,the correction of IR drop becomes a problem of solving nonlinear equations.These equations are practically unsolvable in most cases due to the strictly reduced dynamic range of the effective conductance.We discuss several approaches to this problem,including weight scaling and input-output scaling.The revised experimental demonstration has been validated on the full MNIST(Modified National Institute of Standards and Technology database)test set of 10000 samples,showing only a 0.45%accuracy drop compared to the software baseline.These methods are suitable for both inference and training,and can be integrated into offline tool-chains to provide significant accuracy improvements at minimal cost.4.Decoupling of the analog circuits and the memory array.We propose a working mode of complementary-bit current input and voltage sampling to enable independent design and verification of analog input and analog output.Furthermore,combined with self-aligned output and linear superposition verification,we can guarantee the consistency of linearity metrics on the chip to the greatest extent possible.Using these ideas,we designed a STT-MRAM CIM chip.We also discuss some issues in the architecture design and circuit design of this chip.