| In heterogeneous architectures,the widespread use of hardware accelerators brings improvements in performance and energy efficiency.In the process of designing the accelerator,the high-level synthesis tool can compile the design described in the C language of the accelerator into the Register Transfer Level(RTL)design described in the hardware language.RTL simulation is an important step in functional verification in hardware design.It is used to verify the accelerator design with high accuracy,but it usually takes hours or even days to generate,simulate and analyze a complex accelerator RTL design.However,among the existing RTL simulation acceleration methods,the acceleration method optimized for the analysis process of RTL simulation has a small acceleration multiplier for larger-scale accelerators,and the acceleration method relying on additional hardware is expensive,and the acceleration method that models the performance of the C description of the accelerator has not completed the functional verification of the accelerator circuit design.To solve the above problems,an acceleration method of RTL simulation based on code instrumentation is proposed.Code instrumentation is performed on the C description of the accelerator,so that most of the repeated loop iterations in the accelerator are skipped and not analyzed,and the instrumented C description is compiled into a hardware language description with a high-level synthesis tool,and then perform RTL simulation to achieve a large RTL simulation acceleration multiplier;a performance prediction model is established to predict the number of cycles of the original complete RTL simulation using the RTL simulation performance results of partial loop iterations;variable restoration codes are inserted to ensure the correctness of RTL simulation results,so that the functional verification of the circuit design is completed without using additional hardware,and the performance prediction error is reduced at the same time.In addition,an accelerator design code framework and a series of programming interfaces using this method are designed to facilitate users to efficiently design accelerators using this method,thereby improving the efficiency of accelerator hardware design with high-level synthesis tools.The experimental part uses the Mach Suite accelerator benchmark program to verify the proposed method,and uses Vivado XSIM for RTL simulation.The experimental results show that for the accelerator RTL simulation of single data processing and batch data processing,the average speedup of this method can reach 7.49 and 43.3,respectively,and the average prediction error of the number of cycles for performance is 1.71% and 1.06%,respectively,indicating that this method effectively shortens the time of RTL simulation and controls the low accuracy error.And through experiments,the interval value formula for skipping loop iterations using this method is summarized and deduced,so that users can quickly find the balance area between acceleration multiplier and accuracy when using this method to develop accelerator hardware design. |
