Design Of PAC Coding And Decoding And FPGA Implementation

In the Shannon lecture at the 2019 International Symposium on Information Theory,Arikan proposed a new coding strategy that uses one-to-one convolutional transformations as precoding before polarization transforms,a strategy called polarization-adjusted convolutional codes.In this scheme,the polarization and successive cancellation process are used as preprocessing and post-processing schemes to provide a polarization channel for the convolutional transformation,and the polarization information is provided to the outer code decoder,thereby improving the error correction performance of the outer code.This thesis first introduces the origin of the idea and the research status of the polarizationadjusted convolutional code,and then studies the coding scheme of the polarization-adjusted convolutional code,learns the coding process and rate profile method of the polarizationadjusted convolutional code,and the performance of polarization-adjusted convolutional codes with different rate profile is analyzed.In terms of decoding,this paper focuses on the sequence decoding,using software for performance simulation,and analyzes the performance comparison of the polarization-adjusted convolutional code and the polar code through the simulation results,and then limits the number of searches for the sequence decoding code.The performance of polarization-adjusted convolutional codes under different limits is analyzed.With Vivado as the development platform,the Verilog hardware description language is used to finally complete the FPGA hardware implementation of the polarization-adjusted convolutional code with a code length of 128.Finally,a test platform between the upper computer and the FPGA is built to test the encoder and decoder of the polarization-adjusted convolutional code implemented by the hardware.In terms of encoder,according to the polarization-adjusted convolutional code coding scheme,the overall architecture of the encoder is designed,and from the perspective of hardware implementation,a flexible and variable polarization-adjusted convolutional code encoder structure is designed,which can be applied to encoders of different bit rates according to the input parameters.The resulting encoder,designed with low hardware resource usage,operates stably at a clock frequency of 384.6MHz.In terms of decoder,first,the quantification scheme of the decoder is analyzed,and the overall architecture of the decoder is designed according to the polarization-adjusted convolutional code decoding scheme? secondly,an approximation scheme is used instead of the path metric calculation method to make it easy to implement by hardware? the FPGA implementation of the polarization-adjusted convolutional code is elaborated in detail,and the design scheme of the internal module is introduced systematically.The final design of the decoder can operate stably at clock frequencies up to 250 MHz.Finally,in order to test the encoder and decoder of the polarization-adjusted convolutional code implemented by the hardware,a test platform based on serial port communication and the FPGA is designed,which can easily and quickly verify the correctness of the function of the implemented coder.