Research And Design Of Key Circuits For High-speed Optical Transmitter

With the rapid development and popularization of 5G communication,Internet of Things,Artificial Intelligence,Cloud Computing and other technologies,people have a greater demand for larger capacity and faster communication.Optiacal fiber communication network is the infrastructure for developing the above technologies.As the core chip of the optical fiber communication system,the optical transceiver has a wide range of market demands and research prospects,and has received extensive attention from all walks of life at home and abroad.The SiGe BiCMOS process based on SiGe heterojunction has achieved a good balance between performance and cost due to its high speed and low noise performance advantages,and has become the mainstream process for high-speed chip design.In order to meet the huge market demand for domestic high-speed optoelectronic chips,this thesis designs an input stage circuit for 10Gbps optical transmitter in passive optical networks based on 130nm SiGe BiCMOS process.And based on 180nm SiGe BiCMOS process,a laser driver for 25Gbps optical transmitter for 5G fronthaul is designed.For the design of the 10Gbps optical transmitter,a Continuous Time Linear Equalizer with Load Resistance Compensation is proposed to compensate the high frequency loss of the signal.Based on the CML circuit,a multi-stage cascaded limiting amplifier is designed to receive a wide range of input voltage signals and provide CDR with a fixed amplitude and a limited speed.Through the low-pass sampling method,the DC offset voltage cancellation circuit is designed.The Loss of Signal circuit(LOS)is designed to detect the amplitude of the input signal and output the circuit switch control signal.The layout occupies an area of 0.414 mm2.The simulation results show that the design specifications can be met under the condition of PVT change,the eye opening is good,the LOS can detect the input signal in the range of 20mVpp-80mVpp.The input end is well matched.In the frequency range of 0.01GHz～11.1 GHz,SDD11<-8dB,SCD11<-40dB.Under typical working conditions,the overall power consumption of the circuit is 19.8mW,and the energy efficiency is 1.98pJ/bit,achieving good energy efficiency.For the design of the 25Gbps laser driver,in order to solve the problem of large input capacitance of the main amplifier,the input buffer adopts the negative capacitance technology to expand the bandwidth.The main amplifier adopts a variable power supply voltage and current compensation structure to meet the adjustable requirements of the output modulation current.A multi-level adjustable De-Emphasis circuit is designed to compensate the channel loss and the nonlinearity of the DFB laser.The driver stage adopts a cascode structure with a tail inductance to avoid Miller Capacitance and improve linearity.The output port is DC-coupled with the DFB laser.T-coil network is used to expand bandwidth and improve output port matching."FanOut" Wafer-Level Packaging is used on this chip.The overall transceiver chip area is 8.1 mm2,and the laser driver occupies an area of 0.408 mm2.The test results show that at the rate of 25Gbps,a clear eye diagram with good opening is obtained.The cross point position of the eye diagram is 48%.The rise and fall time is 13.8ps.The jitter is less than 7ps.The Extinction Ratio is 3.58dB.The output end is well matched,in the frequency range of 0.01GHz～25.8GHz,S22<-8dB.The driver output eye diagram passes the mask of the communication standard IEEE 802.3 25GBASE-LR/IEEE 802.325GBASE-ER with a margin of 29%,meeting the communication requirements.