Research And Design Of TOF Readout Circuit For Single-photon LiDAR Based On DLL-TDC

Due to the characteristics of high sensitivity,high speed and high gain of Single Photon Avalanche Diodes(SPAD),SPAD-based photon Time-of-Flight(TOF)Li DAR detection have fast imaging speed and high resolution.It has the potential advantages of fast imaging speed,high resolution and high sensitivity,and has become a radar detection technology that has attracted much attention today,with broad application prospects.However,the TOF readout circuit,as an important part of the SPAD Li DAR detector,still has problems such as low integration,mutual restriction of detection range and distance resolution,low reliability and slow readout speed.Based on the application of LiDAR ranging,this thesis studies and designs a SPAD TOF readout circuit with high time resolution,wide range and high reliability.Firstly,according to the SPAD model,a compact quenching and reset circuit based on passive quenching and active reset is designed.The active reset circuit greatly shortens the reset time of the SPAD device and improves the photon response rate,thereby increasing the readout speed.Secondly,in order to take into account the detection range and time resolution,a two-stage Time-to-Digital Converter(TDC)is proposed.Among them,the counter-type TDC is used in the high segment to expand the detection range.For the inter-segment error problem of the high segment TDC,a pair of differential counters are used to select the readout result to effectively avoid the high segment error;the low segment TDC uses a delay line-based Multi-phase clock interpolation achieves high resolution,obtains stable and uniform multi-phase clock through Delay Locked Loop(DLL)closed-loop feedback control,and uses edge detection to improve low-segment TDC bit errors caused by non-ideal clocks The TDC linearity is improved,and the TOF measurement reliability of the TDC circuit is increased.In addition,a 4-frequency circuit is designed to provide the clock for TDC by using the phase-splitting uniformity of DLL through edge synthesis.Finally,the timing verification of the 8×8 array readout is completed based on the local shared array architecture.Based on the SMIC 0.18 μm standard CMOS process,this thesis uses Cadence virtuoso tools and Xilinx Vivado tools to simulate and verify each module of the circuit,and complete the layout design,post-simulation and tape-out of a single pixel.The overall circuit area is 650 μm×430 μm.The postsimulation results show that under the condition of 1.8 V supply voltage,the peak-to-peak phase jitter of the output clock of the frequency multiplier circuit is 18 ps@75 MHz,and the peak-to-peak jitter of the output split-phase clock of the DLL under the each process is less than 33 ps,which is much lower than the time resolution of TDC and can satisfy the clock requirements of TDC.TDC can achieve a maximum time resolution of 208.3 ps and a maximum dynamic range of 1.2 μs at different input frequencies(50 MHz～75 MHz).The DNL of TDC is less than 0.5 LSB in two different coarse time quantization periods,indicating good linearity of TDC.