Electrically Modeling And Signal Integrity Analysis Of TSV Using Bumpless WOW Technology

Using vertical dimension heterogeneous integration is one of its future development directions,3D IC as its representative technology,effectively reduce the interconnection length,and improve the signal transmission efficiency.At present,the operating frequency of 3DIC presents a trend of diversification.TSV is the key structure of signal transmission channels,electrically modeling is of great significance to the research of TSV.Bumpless interconnects technology reduces the impedance of the TSV interconnects with no bumps and Ultra-thinning of wafers enables maintain total height while supporting more layer counts.Instead of bumps,small TSV passes through the substrate and underfill whose thickness is comparable.Considering this structural feature,the equivalent circuit model of bumpless TSV is proposed and the analytical expressions of the proposed model are studied.Up to 100 GHz,the maximum error of S11 and S21 between proposed model and the physical model built in HFSS less than 3% and 9%.Compared with the traditional TSV equivalent circuit model,the model is more accurate in high frequency.On this basis,the influence of structure size on the S parameter is analyzed by using the control variable method.When the thickness of the filling layer decreases with TSV height,insertion loss and return loss are improved in the whole frequency range.When the substrate thickness decreases with TSV height,the insertion loss increases more greatly due to the increase of substrate conductance.Since the change of substrate thickness is greater than that of traditional TSV,the effect of the decrease of substrate capacitance and TSV inductance on return loss is comparable,resulting in no significant change in return loss.The insertion loss can be improved by increasing the insulation thickness.The proposed model can well estimate the trend of change while scalability is verified.According to the characteristics of technology,the signal integrity of bumpless WOW technology is analyzed.Simulation results show that the MIS effect optimizes channel performance,which is more obvious at low frequency.The contact resistance greatly influences the channel performance,and the insertion loss without bottom cleaning process increases by 6.0554 d B compared with that after bottom cleaning process.The 12-layer stack structure under the HBM2 E standard cannot meet the requirement of signal integrity,so a complete bottom cleaning process is very important for bumpless WOW technology.The channel performance decreases with the increase of stack layers.The bumpless WOW technology can meet the signal integrity requirements of 24 or more stack layers under the HBM2E standard.